公开(公告)号：US20070037342A1

公开(公告)日：2007-02-15

申请号：US11201924

申请日：2005-08-11

申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Joe Tran

发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Joe Tran

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/3205

CPC分类号： H01L21/823425 ,  H01L21/28097 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823443 ,  H01L21/823468 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures 230 include sidewall spacers 515 and have a doped region 525 located between them. A protective layer 710 is placed over the capping layer 610 and the doped region 525, and a portion of the protective layer 710 and capping layer 610 that are located over the gate structures are removed to expose a top surface of the gate structures 230. A remaining portion of the protective layer 710 and capping layer 610 remains over the doped region 525. With the top surface of the gate structures 230 exposed, metal is incorporated into the gate structures to form gate electrodes 230.

摘要翻译： 本发明提供一种制造微电子器件的方法。 在一个方面，该方法包括在位于微电子器件衬底210之上的栅极结构230上形成覆盖层610，其中栅极结构230包括侧壁间隔物515并且具有位于它们之间的掺杂区域525。 保护层710放置在覆盖层610和掺杂区域525上方，并且去除位于栅极结构上方的保护层710和覆盖层610的一部分以露出栅极结构230的顶表面。 保护层710和覆盖层610的剩余部分保留在掺杂区域525上。在栅极结构230的顶表面暴露的情况下，金属被结合到栅极结构中以形成栅电极230。

公开(公告)号：US20100176462A1

公开(公告)日：2010-07-15

申请号：US12731932

申请日：2010-03-25

申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

IPC分类号： H01L29/78

CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.

摘要翻译： 同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。 示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层 所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及 活跃区域。

公开(公告)号：US07727842B2

公开(公告)日：2010-06-01

申请号：US11741519

申请日：2007-04-27

申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

IPC分类号： H01L21/8234

CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.

摘要翻译： 同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。 示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层 所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及 活跃区域。

公开(公告)号：US07396716B2

公开(公告)日：2008-07-08

申请号：US11201924

申请日：2005-08-11

申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Joe G. Tran

发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Joe G. Tran

IPC分类号： H01L21/311

CPC分类号： H01L21/823425 ,  H01L21/28097 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823443 ,  H01L21/823468 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures 230 include sidewall spacers 515 and have a doped region 525 located between them. A protective layer 710 is placed over the capping layer 610 and the doped region 525, and a portion of the protective layer 710 and capping layer 610 that are located over the gate structures are removed to expose a top surface of the gate structures 230. A remaining portion of the protective layer 710 and capping layer 610 remains over the doped region 525. With the top surface of the gate structures 230 exposed, metal is incorporated into the gate structures to form gate electrodes 230.

摘要翻译： 本发明提供一种制造微电子器件的方法。 在一个方面，该方法包括在位于微电子器件衬底210之上的栅极结构230上形成覆盖层610，其中栅极结构230包括侧壁间隔物515并且具有位于它们之间的掺杂区域525。 保护层710放置在覆盖层610和掺杂区域525之上，并且去除位于栅极结构上方的保护层710和覆盖层610的一部分以露出栅极结构230的顶表面。 保护层710和覆盖层610的剩余部分保留在掺杂区域525之上。 在栅极结构230的顶表面暴露的情况下，将金属结合到栅极结构中以形成栅电极230。

公开(公告)号：US20110031557A1

公开(公告)日：2011-02-10

申请号：US12908140

申请日：2010-10-20

申请人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

发明人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

摘要： A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.

摘要翻译： 一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。 栅极电介质层形成在PMOS区域和NMOS区域上。 在栅极电介质层上形成原始栅电极层。 栅极掩模层被施加在栅极电极层上。 蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。 为PMOS器件和NMOS器件形成源极和漏极区域。 为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。 在沟槽中形成包括置换栅极的金属，并且完成IC的制造。

公开(公告)号：US20080265344A1

公开(公告)日：2008-10-30

申请号：US11741519

申请日：2007-04-27

申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.

摘要翻译： 同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。 示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层 所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及 活跃区域。

公开(公告)号：US09035399B2

公开(公告)日：2015-05-19

申请号：US12731932

申请日：2010-03-25

申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Joe G. Tran

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49

CPC分类号： H01L29/665 ,  H01L21/28097 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a first polysilicon layer, a first nitride layer, and a second polysilicon layer), forming a second nitride layer over an active region in the semiconductor substrate adjacent to the gate stack, performing a chemical mechanical polishing that stops on the first nitride layer and on the second nitride layer, removing the first nitride layer and the second nitride layer, and performing a simultaneous silicidation of the first polysilicon layer and the active region.

摘要翻译： 同时硅化半导体器件的多晶硅栅极和源极/漏极的方法以及相关器件。 示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅堆叠包括第一多晶硅层，第一氮化物层和第二多晶硅层），在有源区上形成第二氮化物层 所述半导体衬底与所述栅极堆叠相邻，执行停止在所述第一氮化物层和所述第二氮化物层上的化学机械抛光，去除所述第一氮化物层和所述第二氮化物层，以及执行所述第一多晶硅层的同时硅化;以及 活跃区域。

公开(公告)号：US08574980B2

公开(公告)日：2013-11-05

申请号：US11741551

申请日：2007-04-27

申请人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Craig H. Huffman

发明人： Freidoon Mehrad ,  Shaofeng Yu ,  Steven A. Vitale ,  Craig H. Huffman

IPC分类号： H01L21/8238

CPC分类号： H01L21/823835 ,  H01L21/28097 ,  H01L21/823842 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device. At least some of the illustrative embodiments are methods comprising forming an N-type gate over a semiconductor substrate (the N-type gate having a first thickness), forming a P-type gate over the semiconductor substrate (the P-type gate having a second thickness different than the first thickness), and performing a simultaneous silicidation of the N-type gate and the P-type gate.

摘要翻译： 一种形成具有独立多晶硅栅极厚度的完全硅化的NMOS和PMOS半导体器件的方法及相关器件。 至少一些说明性实施例是包括在半导体衬底（具有第一厚度的N型栅极）上形成N型栅极的方法，在半导体衬底上形成P型栅极（P型栅极具有 第二厚度不同于第一厚度），并且执行N型栅极和P型栅极的同时硅化。

公开(公告)号：US07838356B2

公开(公告)日：2010-11-23

申请号：US12347197

申请日：2008-12-31

申请人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

发明人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

摘要： A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.

摘要翻译： 一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。 栅极电介质层形成在PMOS区域和NMOS区域上。 在栅极电介质层上形成原始栅电极层。 栅极掩模层被施加在栅极电极层上。 蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。 为PMOS器件和NMOS器件形成源极和漏极区域。 为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。 在沟槽中形成包括置换栅极的金属，并且完成IC的制造。

公开(公告)号：US20100164006A1

公开(公告)日：2010-07-01

申请号：US12347197

申请日：2008-12-31

申请人： BRIAN K. KIRKPATRICK ,  Freidoon Mehrad ,  Shaofeng Yu

发明人： BRIAN K. KIRKPATRICK ,  Freidoon Mehrad ,  Shaofeng Yu

IPC分类号： H01L27/088 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

摘要： A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.

摘要翻译： 一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。 栅极电介质层形成在PMOS区域和NMOS区域上。 在栅极电介质层上形成原始栅电极层。 栅极掩模层被施加在栅极电极层上。 蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。 为PMOS器件和NMOS器件形成源极和漏极区域。 为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。 在沟槽中形成包括置换栅极的金属，并且完成IC的制造。