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11.发明申请REPRESENTING AND PROPAGATING A VARIATIONAL VOLTAGE WAVEFORM IN STATISTICAL STATIC TIMING ANALYSIS OF DIGITAL CIRCUITS 有权在数字电路的统计静态时序分析中代表和传播变量电压波形公开(公告)号：US20080250370A1
公开(公告)日：2008-10-09
申请号：US11733058
申请日：2007-04-09
申请人： Soroush Abbaspour , David J. Hathaway , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Soroush Abbaspour , David J. Hathaway , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model.
摘要翻译： 描述了在数字电路的统计静态时序分析中表示和传播变化电压波形的方法。 在一个实施例中，存在用于分析数字电路设计的统计静态时序分析工具。 统计静态时序分析工具包括变分波形建模组件，其被配置为生成近似波形在数字电路节点处的任意波形变换的变分波形模型。 变分波形模型根据考虑在标称波形和扰动波形之间出现的变化的多个波形变换算子将标称波形变换为扰动波形。 变分波形传播分量被配置为根据变化波形模型将变化波形传播通过定时弧从数字电路的至少一个输入到至少一个输出。
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公开(公告)号：US08781792B2
公开(公告)日：2014-07-15
申请号：US12610291
申请日：2009-10-31
IPC分类号： G06F11/30
CPC分类号： G06F17/5045 , G06F2217/10 , G06F2217/82
摘要： Techniques for improving parametric chip yield of manufactured chips are provided. In one aspect, a method for optimizing parametric chip yield is provided. The method includes the following steps. Parametric chip yield is computed based on performance and power consumption of a plurality of manufactured chips subject to a given voltage binning scheme. It is then determined whether the parametric chip yield computed is optimal. If the parametric chip yield is not optimal, the voltage binning scheme is altered and the compute and determine steps are repeated. Otherwise the binning scheme is left unaltered.
摘要翻译： 提供了用于提高制造芯片的参数芯片产量的技术。 在一方面，提供了一种用于优化参数芯片产量的方法。 该方法包括以下步骤。 基于经受给定电压合并方案的多个制造的芯片的性能和功耗来计算参数芯片产量。 然后确定计算的参数芯片产量是否是最佳的。 如果参数芯片产量不是最优的，则改变电压组合方案，并重复计算和确定步骤。 否则，binning方案保持不变。
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13.发明申请公开(公告)号：US20110106483A1
公开(公告)日：2011-05-05
申请号：US12610090
申请日：2009-10-30
CPC分类号： G01R31/31835
摘要： In one embodiment, the invention is a method and apparatus for selecting paths for use in at-speed testing. One embodiment of a method for selecting a set of n paths with which to test an integrated circuit chip includes: organizing the set of n paths into a plurality of sub-sets, receiving a new candidate path, and adding the new candidate path to one of the sub-sets when the new candidate path improves the process coverage metric of the sub-sets.
摘要翻译： 在一个实施例中，本发明是用于选择在速度测试中使用的路径的方法和装置。 用于选择用于测试集成电路芯片的n个路径的集合的方法的一个实施例包括：将n个路径的集合组织成多个子集，接收新的候选路径，并将新的候选路径添加到一个 当新的候选路径改进子集的过程覆盖度量时，子集的子集。
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14.发明授权Representing and propagating a variational voltage waveform in statistical static timing analysis of digital circuits 有权在数字电路的统计静态时序分析中表征和传播变分电压波形公开(公告)号：US07814448B2
公开(公告)日：2010-10-12
申请号：US11733058
申请日：2007-04-09
申请人： Soroush Abbaspour , David J. Hathaway , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Soroush Abbaspour , David J. Hathaway , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An approach that represents and propagates a variational voltage waveform in statistical static timing analysis of digital circuits is described. In one embodiment, there is a statistical static timing analysis tool for analyzing digital circuit designs. The statistical static timing analysis tool includes a variational waveform modeling component that is configured to generate a variational waveform model that approximate arbitrary waveform transformations of waveforms at nodes of a digital circuit. The variational waveform model transforms a nominal waveform into a perturbed waveform in accordance with a plurality of waveform transformation operators that account for variations that occur between the nominal waveform and the perturbed waveform. A variational waveform propagating component is configured to propagate variational waveforms through a timing arc from at least one input to at least one output of the digital circuit in accordance with the variational waveform model.
摘要翻译： 描述了在数字电路的统计静态时序分析中表示和传播变化电压波形的方法。 在一个实施例中，存在用于分析数字电路设计的统计静态时序分析工具。 统计静态时序分析工具包括变分波形建模组件，其被配置为生成近似波形在数字电路节点处的任意波形变换的变分波形模型。 变分波形模型根据考虑在标称波形和扰动波形之间出现的变化的多个波形变换算子将标称波形变换为扰动波形。 变分波形传播分量被配置为根据变化波形模型将变化波形传播通过定时弧从数字电路的至少一个输入到至少一个输出。
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公开(公告)号：US07620921B2
公开(公告)日：2009-11-17
申请号：US11741164
申请日：2007-04-27
申请人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
发明人： Eric A. Foreman , Gary D. Grise , Peter A. Habitz , Vikram Iyengar , David E. Lackey , Chandramouli Visweswariah , Jinjun Xiong , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/10
摘要： Methods, systems and program products for evaluating an IC chip are disclosed. In one embodiment, the method includes running a statistical static timing analysis (SSTA) of a full IC chip design; creating at-functional-speed test (AFST) robust paths for an IC chip, the created robust paths representing a non-comprehensive list of AFST robust paths for the IC chip; and re-running the SSTA with the SSTA delay model setup based on the created robust paths. A process coverage is calculated for evaluation from the SSTA runnings; and a particular IC chip is evaluated based on the process coverage.
摘要翻译： 公开了用于评估IC芯片的方法，系统和程序产品。 在一个实施例中，该方法包括运行全IC芯片设计的统计静态时序分析（SSTA）; 创建用于IC芯片的功能速度测试（AFST）鲁棒路径，所创建的鲁棒路径表示IC芯片的AFST鲁棒路径的非全面列表; 并基于创建的鲁棒路径，使用SSTA延迟模型设置重新运行SSTA。 计算过程覆盖率用于从SSTA运行中进行评估; 并且基于处理覆盖来评估特定的IC芯片。
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16.发明申请公开(公告)号：US20090182522A1
公开(公告)日：2009-07-16
申请号：US12013925
申请日：2008-01-14
CPC分类号： G01R31/31725
摘要： In one embodiment, the invention is a method and apparatus for computing margins for at-speed testing of integrated circuit chips. One embodiment of a method for computing a margin for at-speed testing of an integrated circuit chip design includes computing a statistical chip slack for the chip, computing a statistical test slack for the chip, and computing the margin from the chip slack and the test slack.
摘要翻译： 在一个实施例中，本发明是用于计算集成电路芯片的高速测试的裕量的方法和装置。 用于计算集成电路芯片设计的高速测试的余量的方法的一个实施例包括计算芯片的统计芯片松弛，计算芯片的统计测试松弛，以及从芯片松弛和测试中计算余量 松弛。
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17.发明申请METHOD AND APPARATUS FOR INCREMENTALLY COMPUTING CRITICALITY AND YIELD GRADIENT 有权用于更严格地计算关键度和等级的方法和装置公开(公告)号：US20090100393A1
公开(公告)日：2009-04-16
申请号：US11870672
申请日：2007-10-11
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031
摘要： In one embodiment, the invention is a method and apparatus for incrementally computing criticality and yield gradient. One embodiment of a method for computing a diagnostic metric for a circuit includes modeling the circuit as a timing graph, determining a chip slack for the circuit, determining a slack of at least one diagnostic entity, and computing a diagnostic metric relating to the diagnostic entity(ies) from the chip slack and the slack of the diagnostic entity(ies).
摘要翻译： 在一个实施例中，本发明是用于递增地计算临界度和屈服梯度的方法和装置。 用于计算电路的诊断度量的方法的一个实施例包括将电路建模为定时图，确定电路的芯片松弛，确定至少一个诊断实体的松弛，以及计算与诊断实体有关的诊断度量 （ies）从芯片松弛和诊断实体的松弛。
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18.发明授权Method and apparatus for covering a multilayer process space during at-speed testing 有权在高速测试期间覆盖多层工艺空间的方法和装置公开(公告)号：US07971120B2
公开(公告)日：2011-06-28
申请号：US12340072
申请日：2008-12-19
IPC分类号： G06F11/00
CPC分类号： G01R31/2882
摘要： In one embodiment, the invention is a method and apparatus covering a multilayer process space during at-speed testing. One embodiment of a method for selecting a set of paths with which to test a process space includes determining a number N of paths to be included in the set of paths such that at least number M of paths in N for which testing of the process space will fail, computing a metric that substantially ensures that the set of paths satisfies the requirements of N and M, and outputting the metric for use in selecting the set of paths.
摘要翻译： 在一个实施例中，本发明是在高速测试期间覆盖多层工艺空间的方法和装置。 用于选择用于测试处理空间的一组路径的方法的一个实施例包括确定要包括在路径集合中的路径数量N，使得至少数目M的路径在其中用于对进程空间进行测试 将会失败，计算基本上确保路径组满足N和M的要求并输出用于选择路径集合的度量的度量。
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19.发明授权公开(公告)号：US07873925B2
公开(公告)日：2011-01-18
申请号：US12013925
申请日：2008-01-14
IPC分类号： G06F17/50
CPC分类号： G01R31/31725
摘要： In one embodiment, the invention is a method and apparatus for computing margins for at-speed testing of integrated circuit chips. One embodiment of a method for computing a margin for at-speed testing of an integrated circuit chip design includes computing a statistical chip slack for the chip, computing a statistical test slack for the chip, and computing the margin from the chip slack and the test slack.
摘要翻译： 在一个实施例中，本发明是用于计算集成电路芯片的高速测试的裕量的方法和装置。 用于计算集成电路芯片设计的高速测试的余量的方法的一个实施例包括计算芯片的统计芯片松弛，计算芯片的统计测试松弛，以及从芯片松弛和测试中计算余量 松弛。
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公开(公告)号：US20110106497A1
公开(公告)日：2011-05-05
申请号：US12610291
申请日：2009-10-31
IPC分类号： G21C17/00
CPC分类号： G06F17/5045 , G06F2217/10 , G06F2217/82
摘要： Techniques for improving parametric chip yield of manufactured chips are provided. In one aspect, a method for optimizing parametric chip yield is provided. The method includes the following steps. Parametric chip yield is computed based on performance and power consumption of a plurality of manufactured chips subject to a given voltage binning scheme. It is then determined whether the parametric chip yield computed is optimal. If the parametric chip yield is not optimal, the voltage binning scheme is altered and the compute and determine steps are repeated. Otherwise the binning scheme is left unaltered.
摘要翻译： 提供了用于提高制造芯片的参数芯片产量的技术。 在一个方面，提供了一种用于优化参数芯片产量的方法。 该方法包括以下步骤。 基于经受给定电压合并方案的多个制造的芯片的性能和功耗来计算参数芯片产量。 然后确定计算的参数芯片产量是否是最佳的。 如果参数芯片产量不是最优的，则改变电压组合方案，并重复计算和确定步骤。 否则，binning方案保持不变。
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