公开(公告)号：US20200350420A1

公开(公告)日：2020-11-05

申请号：US16957600

申请日：2018-11-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang CHENG ,  Yan GU ,  Sen ZHANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L21/265 ,  H01L21/266

Abstract: A method for manufacturing a semiconductor device and an integrated semiconductor device, said method comprising: providing an epitaxial layer having a first region and a second region, forming, in the first region, at least two second doping-type deep wells, and forming, in the second region, at least two second doping-type deep wells; forming a first dielectric island between the second doping-type deep wells and forming a second dielectric island on the second doping-type deep wells; forming a first doping-type trench on two sides of the first dielectric island in the first region; forming a gate structure on the first dielectric island; and forming a separated first doping-type source region by using the second dielectric island as a mask, the first doping-type trench extending, in the first region, transversally to the first doping-type source region.

公开(公告)号：US20200335498A1

公开(公告)日：2020-10-22

申请号：US16755817

申请日：2018-11-21

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Shikang CHENG ,  Yan GU ,  Sen ZHANG

IPC: H01L27/088 ,  H01L29/78

Abstract: The present application provides an integrated semiconductor device and an electronic apparatus, comprising a semiconductor substrate and a first doped epitaxial layer having a first region, a second region, and a third region; a partition structure is arranged in the third region; the first region is formed having at least two second doped deep wells, and the second region is formed having at least two second doped deep wells; a dielectric island partially covers a region between two adjacent doped deep wells in the first region and second region; a gate structure covers the dielectric island; a first doped source region is located on the two sides of the gate structure, and a first doped source region located in the same second doped deep well is separated; a first doped trench is located on the two sides of the dielectric island in the first region, and extends laterally to the first doped source region.

公开(公告)号：US20200258782A1

公开(公告)日：2020-08-13

申请号：US16643170

申请日：2018-08-31

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Lihui GU ,  Sen ZHANG ,  Congming QI

IPC: H01L21/8249 ,  H01L29/739 ,  H01L29/78 ,  H01L27/06

Abstract: An integrated circuit chip and a manufacturing method therefor, and a gate drive circuit, the integrated circuit chip comprising: a semiconductor substrate (103), a high voltage island (101a) being formed in the semiconductor substrate (103); a high voltage junction terminal (102a), the high voltage junction terminal (102a) surrounding the high voltage island (101a), a depletion type MOS device (N1) being formed on the high voltage junction terminal (102a), a gate electrode and a drain electrode of the depletion type MOS device (N1) being short connected, and a source electrode of the depletion type MOS device (N1) being connected to a high side power supply end (VB) of the integrated circuit chip; and a bipolar transistor (Q1), a collector electrode of the bipolar transistor (Q1) being short connected to the substrate and being connected to a low side power supply end (VCC) of the integrated circuit chip, an emitter of the bipolar transistor (Q1) being connected to a gate electrode of the depletion type MOS device (N1).

公开(公告)号：US20190259669A1

公开(公告)日：2019-08-22

申请号：US16329550

申请日：2017-08-31

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan GU ,  Shikang CHENG ,  Sen ZHANG

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/808 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66 ,  H01L29/45 ,  H01L21/306 ,  H01L29/40 ,  H01L27/06

Abstract: A device integrated with JFET, the device is divided into a JFET region and a power device region, and the device includes: a drain (201) with a first conduction type; and a first conduction type region disposed on a front surface of the drain (201); the JFET region includes: a first well (205) with a second conduction type and formed in the first conduction type region; a second well (207) with a second conduction type and formed in the first conduction type region; a JFET source (212) with the first conduction type; a metal electrode formed on the JFET source (212), which is in contact with the JFET source (212); and a second conduction type buried layer (203) formed under the JFET source (212) and the second well (207).

公开(公告)号：US20180012980A1

公开(公告)日：2018-01-11

申请号：US15548290

申请日：2016-01-28

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan GU ,  Wei SU ,  Sen ZHANG

IPC: H01L29/739 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7394 ,  H01L29/1037 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/735

Abstract: A lateral insulated gate bipolar transistor, comprising: a substrate (100), having a first conductivity type; an insulating layer (200), formed on the substrate (100); an epitaxial layer (300), having a second conductivity type and formed on the insulating layer (200); a field oxide layer (400), formed on the epitaxial layer (300); a first well (500), having the first conductivity type; a plurality of gate trench structures (600); second source doped regions (720), having the second conductivity type; first source doped regions (710), having the first conductivity type; a second well (800), having the second conductivity type; a first drain doped region (910), having the first conductivity type and formed on a surface layer of the second well (800); gate lead-out ends (10); a source lead-out end (20); a drain lead-out end (30).

公开(公告)号：US20250056834A1

公开(公告)日：2025-02-13

申请号：US18722930

申请日：2022-11-30

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO LTD.

Inventor： Long ZHANG ,  Nailong HE ,  Yongjiu CUI ,  Sen ZHANG ,  Xiaona WANG ,  Feng LIN ,  Jie MA ,  Siyang LIU ,  Weifeng SUN

IPC: H01L29/78 ,  H01L21/266 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: A manufacturing method for a P-type laterally diffused metal oxide semiconductor device includes: forming a N-type buried layer in a substrate, forming a P-type region located on the N-type buried layer, and forming a mask layer located on the P-type region; patterning the mask layer to form at least two injection windows; performing N-type ion implantation by the at least two injection windows; forming an oxide layer; removing the mask layer; performing P-type ion implantation on the P-type region to form a P-type doped region; diffusing the P-type doped region to form a drift region and two P-type well regions, diffusing the high-voltage N-well doped region to form a high-voltage N-type well region, and diffusing the low-voltage N-well doped region to form a low-voltage N-type well region; and forming a source doped region, a drain doped region, and a gate.

公开(公告)号：US20240072178A1

公开(公告)日：2024-02-29

申请号：US18262083

申请日：2022-03-03

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Yan GU ,  Hua SONG ,  Nailong HE ,  Sen ZHANG

IPC: H01L29/872 ,  H01L29/40 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/872 ,  H01L29/404 ,  H01L29/66143 ,  H01L29/66659 ,  H01L29/7394 ,  H01L29/7835

Abstract: A diode and a manufacturing method therefor, and a semiconductor device. The diode includes: a substrate; an insulating buried layer provided on the substrate; a semiconductor layer provided on the insulating buried layer; anode; and a cathode, comprising: a trench-type contact, a trench being filled with a contact material, the trench extending from a first surface of the semiconductor layer to a second surface of the semiconductor layer, the first surface being a surface distant from the insulating buried layer, and the second surface being a surface facing the insulating buried layer; a cathode doped region surrounding the trench-type contact around and at the bottom of the trench-type contact, and also disposed on the first surface around the trench-type contact; and a negative electrode located on the cathode doped region and electrically connected to the cathode doped region.

公开(公告)号：US20230146299A1

公开(公告)日：2023-05-11

申请号：US17912760

申请日：2021-07-02

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jingchuan ZHAO ,  Nailong HE ,  Sen ZHANG ,  Zhili ZHANG ,  Hao WANG

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/7816 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/66681

Abstract: A laterally diffused metal-oxide-semiconductor (LDMOS) device and a method for fabricating the LDMOS device are disclosed. The device includes: a substrate (101) having a second conductivity type; a drift region (102) that has a first conductivity type and is disposed on the substrate (101), wherein the first conductivity type is opposite to the second conductivity type; a plurality of layers of doped structures disposed in the drift region (102), each layer of the doped structure comprising at least one doped bar (105) extending in a lengthwise direction of a conductive channel; and a plurality of doped polysilicon pillars (106) disposed in the drift region (102) so as to extend downward through the doped bar (105) of at least one of the layer of doped structures, wherein ions doped in the doped polysilicon pillars (106) and ions doped in the doped bar have opposite conductivity types.

公开(公告)号：US20220359673A1

公开(公告)日：2022-11-10

申请号：US17623485

申请日：2020-05-26

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Jingchuan ZHAO ,  Zhili ZHANG ,  Sen ZHANG

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

Abstract: A laterally diffused metal oxide semiconductor device and a manufacturing method thereof. The device includes: a substrate of a second conductivity type; a drift region arranged on the substrate and of a first conductivity type; a source region of the first conductivity type; a drain region of the first conductivity type; and a longitudinal floating field plate structure arranged between the source region and the drain region and including a dielectric layer arranged on an inner surface of a trench and polysilicon filling the trench. The trench extends from an upper surface of the drift region downward through the drift region into the substrate. At least two longitudinal floating field plate structures are provided, and at least two of the longitudinal floating field plate structures are located at different positions in a length direction of a conductive channel.

公开(公告)号：US20210036150A1

公开(公告)日：2021-02-04

申请号：US16645139

申请日：2018-09-01

Applicant: CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Nailong HE ,  Sen ZHANG ,  Xuchao LI

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06

Abstract: A lateral double-diffused metal oxide semiconductor component and a manufacturing method therefor. The lateral double-diffused metal oxide semiconductor component comprises: a semiconductor substrate, the semiconductor substrate being provided thereon with a drift area; the drift area being provided therein with a trap area and a drain area, the trap area being provided therein with an active area and a channel; the drift area being provided therein with a deep trench isolation structure arranged between the trap area and the drain area, and the deep trench isolation structure being provided at the bottom thereof with alternately arranged first p-type injection areas and first n-type injection areas.