公开(公告)号：US20220376094A1

公开(公告)日：2022-11-24

申请号：US17762212

申请日：2020-08-26

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

Inventor： Long ZHANG ,  Jie MA ,  Yan GU ,  Sen ZHANG ,  Jing ZHU ,  Jinli GONG ,  Weifeng SUN ,  Longxing SHI

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

Abstract: An insulated gate bipolar transistor, comprising an anode second conductivity-type region and an anode first conductivity-type region provided on a drift region; the anode first conductivity-type region comprises a first region and a second region, and the anode second conductivity-type region comprises a third region and a fourth region, the dopant concentration of the first region being less than that of the second region, the dopant concentration of the third region being less than that of the fourth region, the third region being provided between the fourth region and a body region, the first region being provided below the fourth region, and the second region being provided below the third region and located between the first region and the body region.

公开(公告)号：US20250056834A1

公开(公告)日：2025-02-13

申请号：US18722930

申请日：2022-11-30

Applicant: SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO LTD.

Inventor： Long ZHANG ,  Nailong HE ,  Yongjiu CUI ,  Sen ZHANG ,  Xiaona WANG ,  Feng LIN ,  Jie MA ,  Siyang LIU ,  Weifeng SUN

IPC: H01L29/78 ,  H01L21/266 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: A manufacturing method for a P-type laterally diffused metal oxide semiconductor device includes: forming a N-type buried layer in a substrate, forming a P-type region located on the N-type buried layer, and forming a mask layer located on the P-type region; patterning the mask layer to form at least two injection windows; performing N-type ion implantation by the at least two injection windows; forming an oxide layer; removing the mask layer; performing P-type ion implantation on the P-type region to form a P-type doped region; diffusing the P-type doped region to form a drift region and two P-type well regions, diffusing the high-voltage N-well doped region to form a high-voltage N-type well region, and diffusing the low-voltage N-well doped region to form a low-voltage N-type well region; and forming a source doped region, a drain doped region, and a gate.

公开(公告)号：US20240266430A1

公开(公告)日：2024-08-08

申请号：US18577714

申请日：2022-12-29

Applicant: SOUTHEAST UNIVERSITY

Inventor： Long ZHANG ,  Weifeng SUN ,  Siyang LIU ,  Jie MA ,  Peigang LIU ,  Longxing SHI

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/20 ,  H01L29/207

CPC classification number: H01L29/7787 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/207

Abstract: An enhancement-mode N-channel and P-channel GaN device integration structure comprises a substrate, wherein an Al—N nucleating layer, an AlGaN buffer layer, a GaN channel layer and an AlGaN barrier layer are sequentially arranged on the substrate, and the AlGaN barrier layer and the GaN channel layer are divided by an isolation layer; a P-channel device is arranged on one side of the isolation layer and comprises a first P-GaN layer, a first GaN isolation layer and a first P+-GaN layer are sequentially arranged on the first P-GaN layer, a first source, a first gate and a first drain are arranged on the first P+-GaN layer, the first gate is inlaid in the first P+-GaN layer, and a gate dielectric layer is arranged between the first gate and the first P+-GaN layer; and an N-channel device is arranged on the other side of the isolation layer.

公开(公告)号：US20250155525A1

公开(公告)日：2025-05-15

申请号：US18849562

申请日：2024-03-18

Applicant: SOUTHEAST UNIVERSITY

Inventor： Long ZHANG ,  Weifeng SUN ,  Siyang LIU ,  Guiqiang ZHENG ,  Yichen LI ,  Xueqi LI ,  Longxing SHI

IPC: G01R33/00 ,  G01R33/07 ,  H01L21/762 ,  H10N52/01 ,  H10N52/80

Abstract: A horizontal Hall device includes a substrate layer and a BOX layer arranged on the substrate layer, where an epitaxial layer is arranged on the BOX layer, a well layer is arranged on the epitaxial layer, an STI layer is arranged on the well layer, a pair of induction electrodes and a pair of bias electrodes are arranged on the STI layer, ground electrodes are arranged on the epitaxial layer, and current barrier layers are arranged between the induction electrodes and the adjacent bias electrodes.

公开(公告)号：US20220157975A1

公开(公告)日：2022-05-19

申请号：US17606216

申请日：2020-03-31

Applicant: SOUTHEAST UNIVERSITY

Inventor： Jing ZHU ,  Ankang LI ,  Long ZHANG ,  Weifeng SUN ,  Shengli LU ,  Longxing SHI

IPC: H01L29/739 ,  H01L29/10

Abstract: A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer. The polysilicon gate includes a first gate located above the surface of the P-type body region and a second gate located above the pinch-off region and the N-type drift region. The first gate is connected to a first gate resistor, and the second gate is connected to a second gate resistor.