Abstract:
A CMOS image sensor and a manufacturing method are disclosed. The gates of the transistors are formed in the active region of the unit pixel, and a diffusion region for the photo diode is defined by an ion implantation of impurities to the semiconductor substrate. The patterns of the photoresist that are the masking layer against ion implantation are formed on the semiconductor substrate in such a manner that they have the boundary portion of the isolation layer so as not to make the boundary of the defined photo diode contact with the boundary of the isolation layer. Damages by an ion implantation of impurities at the boundary portion between the diffusion region for the photo diode and the isolation layer are prevented, which reduces dark current of the COMS image sensor.
Abstract:
CMOS image sensor and method for fabricating the same, the CMOS image sensor including a second conductive type semiconductor substrate having an active region and a device isolation region defined therein, wherein the active region has a photodiode region and a transistor region defined therein, a device isolating film in the semiconductor substrate of the device isolation region, a first conductive type impurity region in the semiconductor substrate of the photodiode region, the first conductive type impurity region being spaced a distance from the device isolation film, and a second conductive type first impurity region in the semiconductor substrate between the first conductive type impurity region and the device isolation film, thereby reducing generation of a darkcurrent at an interface between the photodiode region and a field region.
Abstract:
A CMOS image sensor includes a first conductive type semiconductor substrate having an active region and a device isolation region, a device isolation film formed in the device isolation region of the semiconductor substrate, a second conductive type diffusion region formed in the active region of the semiconductor substrate, and an ion implantation prevention layer formed in the vicinity of the device isolation film, including a boundary portion between the device isolation film and the second conductive type diffusion region.
Abstract:
A flash memory device having a reduced source resistance and a fabrication method thereof are disclosed. An example flash memory includes a cell region including a gate, a source line, a drain contact, and a cell trench area for device isolation on a silicon substrate. The example flash memory also includes a peripheral region positioned around the cell region and including a subsidiary circuit and a peripheral trench area for device isolation on the silicon substrate, wherein the cell trench area of the cell region is shallower than the peripheral trench area of the peripheral region.
Abstract:
Disclosed is a method for fabricating a silicide layer of a flat cell memory device. The disclosed method comprises the steps of: providing a silicon substrate whereon a flat cell array region and a peripheral circuit region are defined; forming a word line and a bit diffusion layer on the flat cell array region of the substrate and a word line and source/drain junction on the peripheral circuit region; forming a gap fill insulating layer to fill up the gap between the word lines; removing the gap fill insulating layer on the peripheral circuit region; forming an insulating layer on the whole substrate; dry etching the insulating layer to expose a surface of word line, and a surface of the substrate of the peripheral circuit region, thereby forming a spacer on a side wall of the word line of the peripheral circuit region; and forming a silicide layer on the upper part of the word line of the flat cell array region and, at the same time, forming a salicide layer on the upper part of the word line and the surface of the substrate of the peripheral circuit region.
Abstract:
Disclosed is an image sensor. The image sensor includes a semiconductor substrate including unit pixels, an interlayer dielectric layer including metal interconnections formed on the semiconductor substrate, a plurality of bottom electrodes formed on the interlayer dielectric layer in correspondence with the unit pixels, the plurality of bottom electrodes includes bottom electrodes having at least two different sizes, a photodiode formed on the interlayer dielectric layer including the bottom electrodes, and color filters formed on the photodiode in correspondence with the unit pixels.
Abstract:
A CMOS image sensor and method for fabricating the same, wherein the CMOS image sensor has minimized dark current at the boundary area between a photodiode and an isolation layer. The present invention includes a first-conductivity-type doping area formed in the device isolation area of the substrate, the first-conductivity-type doping area surrounding the isolation area and a dielectric layer formed between the isolation layer and the first-conductivity-type doping area, wherein the first-conductivity-type doping area and the dielectric layer are located between the isolation layer and a second-conductivity-type diffusion area.
Abstract:
A method for manufacturing a CMOS image sensor is provided. The method can include forming an interlayer dielectric layer on a semiconductor substrate including a gate electrode, photodiode area, and LDD region; selectively removing the interlayer dielectric layer such that the interlayer dielectric layer remains on the photodiode area; performing a first heat treatment process; sequentially forming a first insulating layer and a second insulating layer on the semiconductor substrate, where the etching selectivity of the first insulating layer is different from the etching selectivity of the second insulating layer; selectively etching the second insulating layer to form spacers on sidewalls of the gate electrode; selectively removing the first insulating layer to expose a source/drain area and forming a high-density N-type diffusion area in the exposed source/drain area; performing a second heat treatment process; and forming a metal silicide layer the high-density N-type diffusion area.
Abstract:
Disclosed are a CMOS image sensor and a manufacturing method thereof. The present CMOS image sensor comprises: first, second, and third photo diodes and a plurality of transistors spaced at a predetermined distance in a semiconductor substrate; a diffusion blocking layer on substantially an entire surface of the substrate, including an opening therein exposing at least one of the photo diodes; an interlevel dielectric layer over the entire surface of the substrate, covering the diffusion blocking layer; first, second and third color filter layers over the interlevel dielectric layer, respectively corresponding to the first, second and third photo diodes, and a plurality of microlenses over the color filter layers, corresponding to each color filter layer.
Abstract:
A CMOS image sensor and method of manufacturing the same are provided. In one embodiment, the CMOS image sensor includes: an interlayer dielectric layer formed on a semiconductor substrate including a plurality of photodiodes and transistors; a plurality of color filter isolation layers formed on the interlayer dielectric layer; a color filter layer comprising a first color filter, a second color filter, and a third color filter formed on the interlayer dielectric layer, wherein a portion of the first color filter and a portion of the second color filter are formed on one of the plurality of color filter isolation layers, and wherein a portion of the second color filter and a portion of the third color filter are formed on another of the plurality of color filter isolation layers; and microlenses formed on the color filter layer.