公开(公告)号：US20150364460A1

公开(公告)日：2015-12-17

申请号：US14728189

申请日：2015-06-02

申请人： Tsung-Yi Huang ,  Kuo-Hsuan Lo ,  Wu-Te Weng

发明人： Tsung-Yi Huang ,  Kuo-Hsuan Lo ,  Wu-Te Weng

IPC分类号： H01L27/02 ,  H01L29/66 ,  H01L21/762 ,  H01L29/866

CPC分类号： H01L27/0255 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/66106 ,  H01L29/66136 ,  H01L29/861 ,  H01L29/866

摘要： The present invention discloses a transient voltage suppression (TVS) device and a manufacturing method thereof. The TVS device limits a voltage drop between two terminals thereof not to exceed a clamp voltage. The TVS device is formed in a stack substrate including a semiconductor substrate, a P-type first epitaxial layer, and a second epitaxial layer stacked in sequence. In the TVS device, a first PN diode is connected to a Zener diode in series, wherein the series circuit is surrounded by a first shallow trench isolation (STI) region; and a second PN diode is connected in parallel to the series circuit, wherein the second PN diode is surrounded by a second STI region. The first STI region and the second STI region both extend from an upper surface to the second epitaxial layer, but not to the first epitaxial layer.

摘要翻译： 本发明公开了一种瞬态电压抑制（TVS）装置及其制造方法。 TVS器件限制其两个端子之间的电压降不超过钳位电压。 TVS器件形成在堆叠衬底中，该衬底包括依次层叠的半导体衬底，P型第一外延层和第二外延层。 在TVS器件中，第一PN二极管串联连接到齐纳二极管，其中串联电路由第一浅沟槽隔离（STI）区域包围; 并且第二PN二极管与串联电路并联连接，其中第二PN二极管被第二STI区域包围。 第一STI区域和第​​二STI区域都从上表面延伸到第二外延层，而不是延伸到第一外延层。

公开(公告)号：US09105757B2

公开(公告)日：2015-08-11

申请号：US14040670

申请日：2013-09-28

申请人： Chih-Fang Huang ,  Tsung-Yi Huang ,  Chien-Wei Chiu ,  Tsung-Yu Yang ,  Ting-Fu Chang ,  Tsung-Chieh Hsiao ,  Ya-Hsien Liu ,  Po-Chin Peng

发明人： Chih-Fang Huang ,  Tsung-Yi Huang ,  Chien-Wei Chiu ,  Tsung-Yu Yang ,  Ting-Fu Chang ,  Tsung-Chieh Hsiao ,  Ya-Hsien Liu ,  Po-Chin Peng

IPC分类号： H01L29/872 ,  H01L29/66 ,  H01L29/868 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66212

摘要： The present invention discloses a junction barrier Schottky (JBS) diode and a manufacturing method thereof. The JBS diode includes: an N-type gallium nitride (GaN) substrate; an aluminum gallium nitride (AlGaN) barrier layer, which is formed on the N-type GaN substrate; a P-type gallium nitride (GaN) layer, which is formed on or above the N-type GaN substrate; an anode conductive layer, which is formed at least partially on the AlGaN barrier layer, wherein a Schottky contact is formed between part of the anode conductive layer and the AlGaN barrier layer; and a cathode conductive layer, which is formed on the N-type GaN substrate, wherein an ohmic contact is formed between the cathode conductive layer and the N-type GaN substrate, and the cathode conductive layer is not directly connected to the anode conductive layer.

摘要翻译： 本发明公开了一种接合势垒肖特基（JBS）二极管及其制造方法。 JBS二极管包括：N型氮化镓（GaN）衬底; 形成在N型GaN衬底上的氮化镓铝（AlGaN）阻挡层; 在N型GaN衬底上形成的P型氮化镓（GaN）层; 至少部分地形成在AlGaN阻挡层上的阳极导电层，其中在所述阳极导电层的一部分和所述AlGaN阻挡层之间形成肖特基接触; 以及阴极导电层，其形成在N型GaN衬底上，其中在阴极导电层和N型GaN衬底之间形成欧姆接触，并且阴极导电层不直接连接到阳极导电层 。

公开(公告)号：US09105656B2

公开(公告)日：2015-08-11

申请号：US14055622

申请日：2013-10-16

申请人： Tsung-Yi Huang ,  Kuo-Hsuan Lo

发明人： Tsung-Yi Huang ,  Kuo-Hsuan Lo

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/337 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC分类号： H01L29/66681 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/7835

摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate in which isolation regions are formed for defining a device region; agate formed on the first conductive type substrate; a source and a drain formed in the device region and located at both sides of the gate respectively, and doped with second conductive type impurities; a second conductive type well, which is formed in the first conductive type substrate, and surrounds the drain from top view; and a first deep trench isolation structure, which is formed in the first conductive type substrate, and is located in the second conductive type well between the source and the drain from top view, wherein the depth of the first deep trench isolation structure is deeper than the second conductive type well from the cross-sectional view.

摘要翻译： 本发明公开了一种高压器件及其制造方法。 高压器件包括：第一导电型衬底，其中形成隔离区以限定器件区域; 形成在第一导电类型衬底上的玛瑙; 在器件区域中分别形成并位于栅极两侧的源极和漏极，并掺杂有第二导电类型杂质; 第二导电型阱，其形成在第一导电类型基板中，并且从俯视图围绕漏极; 以及第一深沟槽隔离结构，其形成在第一导电类型基板中，并且从顶视图位于源极和漏极之间的第二导电类型阱中，其中第一深沟槽隔离结构的深度比 第二导电类型井从横截面图。

公开(公告)号：US20150091104A1

公开(公告)日：2015-04-02

申请号：US14041336

申请日：2013-09-30

申请人： Tsung-Yi Huang

发明人： Tsung-Yi Huang

IPC分类号： H01L29/06 ,  H01L29/78

CPC分类号： H01L29/0684 ,  H01L21/823892 ,  H01L29/0646 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/78 ,  H01L29/7816

摘要： The invention provides a semiconductor structure and a semiconductor device having such semiconductor structure. The semiconductor structure includes: a substrate; a first well having a first conductivity type, which is provided on the substrate; a second well having a second conductivity type and contacting the first well at a boundary in between in a lateral direction; and a plurality of mitigation regions having the first conductivity type or the second conductivity type, provided in the first well and being close to the boundary in a lateral direction and penetrating the first well in a vertical direction.

摘要翻译： 本发明提供一种具有这种半导体结构的半导体结构和半导体器件。 半导体结构包括：基板; 具有第一导电类型的第一阱，其设置在基板上; 第二阱具有第二导电类型，并且在横向方向上的边界处接触第一阱; 以及具有第一导电类型或第二导电类型的多个缓和区，设置在第一阱中并且在横向方向上接近边界并且在垂直方向上穿透第一阱。

公开(公告)号：US20140315358A1

公开(公告)日：2014-10-23

申请号：US13866766

申请日：2013-04-19

申请人： Tsung-Yi Huang ,  Chien-Hao Huang

发明人： Tsung-Yi Huang ,  Chien-Hao Huang

IPC分类号： H01L29/66

CPC分类号： H01L29/66893 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/66901 ,  H01L29/808

摘要： The present invention discloses a manufacturing method of a junction field effect transistor (JFET). The manufacturing method includes: providing a substrate with a first conductive type, forming a channel region with a second conductive type, forming a field region with the first conductive type, forming a gate with the first conductive type, forming a source with the second conductive type, forming a drain with the second conductive type, and forming a lightly doped region with the second conductive type. The channel region is formed by an ion implantation process step, wherein the lightly doped region is formed by masking a predetermined region from accelerated ions of the ion implantation process step, and diffusing impurities with the second conductive type nearby the predetermined region into it with a thermal process step.

摘要翻译： 本发明公开了一种结型场效应晶体管（JFET）的制造方法。 该制造方法包括：提供具有第一导电类型的衬底，形成具有第二导电类型的沟道区，形成具有第一导电类型的场区，形成具有第一导电类型的栅极，形成具有第二导电 形成具有第二导电类型的漏极，以及形成具有第二导电类型的轻掺杂区域。 沟道区域通过离子注入工艺步骤形成，其中通过从离子注入工艺步骤的加速离子掩蔽预定区域并且将具有第二导电类型的杂质附近的预定区域的杂质扩散到其中以通过离子注入工艺步骤 热处理步骤。

公开(公告)号：US08729630B1

公开(公告)日：2014-05-20

申请号：US14146512

申请日：2014-01-02

申请人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L29/66

CPC分类号： H01L29/4238 ,  H01L21/28114 ,  H01L21/823425 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

公开(公告)号：US08686504B2

公开(公告)日：2014-04-01

申请号：US13555163

申请日：2012-07-22

申请人： Tsung-Yi Huang ,  Chien-Hao Huang

发明人： Tsung-Yi Huang ,  Chien-Hao Huang

IPC分类号： H01L29/66

CPC分类号： H01L29/78 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816

摘要： The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively.

公开(公告)号：US08643136B2

公开(公告)日：2014-02-04

申请号：US13037678

申请日：2011-03-01

申请人： Tsung-Yi Huang ,  Kuo-Hsuan Lo

发明人： Tsung-Yi Huang ,  Kuo-Hsuan Lo

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/66681 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/7835

摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate in which isolation regions are formed for defining a device region; a gate formed on the first conductive type substrate; a source and a drain formed in the device region and located at both sides of the gate respectively, and doped with second conductive type impurities; a second conductive type well, which is formed in the first conductive type substrate, and surrounds the drain from top view; and a first deep trench isolation structure, which is formed in the first conductive type substrate, and is located in the second conductive type well between the source and the drain from top view, wherein the depth of the first deep trench isolation structure is deeper than the second conductive type well from the cross-sectional view.

摘要翻译： 本发明公开了一种高压器件及其制造方法。 高压器件包括：第一导电型衬底，其中形成隔离区以限定器件区域; 形成在所述第一导电型基板上的栅极; 在器件区域中分别形成并位于栅极两侧的源极和漏极，并掺杂有第二导电类型杂质; 第二导电型阱，其形成在第一导电类型基板中，并且从俯视图围绕漏极; 以及第一深沟槽隔离结构，其形成在第一导电类型基板中，并且从顶视图位于源极和漏极之间的第二导电类型阱中，其中第一深沟槽隔离结构的深度比 第二导电类型井从横截面图。

公开(公告)号：US20130299840A1

公开(公告)日：2013-11-14

申请号：US13466550

申请日：2012-05-08

申请人： Chieh-Hsiung Kuan ,  Ting-Wei Liao ,  Chien-Wei Chiu ,  Tsung-Yi Huang

发明人： Chieh-Hsiung Kuan ,  Ting-Wei Liao ,  Chien-Wei Chiu ,  Tsung-Yi Huang

IPC分类号： H01L29/20 ,  H01L21/28 ,  H01L29/872

CPC分类号： H01L29/417 ,  H01L29/2003 ,  H01L29/413 ,  H01L29/66212 ,  H01L29/872

摘要： The present invention discloses a Schottky barrier diode (SBD) and a manufacturing method thereof. The SBD includes: a semiconductor layer, which has multiple openings forming an opening array; and an anode, which has multiple conductive protrusions protruding into the multiple openings and forming a conductive array; wherein a Schottky contact is formed between the semiconductor layer and the anode.

摘要翻译： 本发明公开了一种肖特基势垒二极管（SBD）及其制造方法。 SBD包括：半导体层，其具有形成开口阵列的多个开口; 以及阳极，其具有突出到所述多个开口中并形成导电阵列的多个导电突起; 其中在所述半导体层和所述阳极之间形成肖特基接触。

公开(公告)号：US20130045577A1

公开(公告)日：2013-02-21

申请号：US13317568

申请日：2011-10-21

申请人： Tsung-Yi Huang ,  Yuh-Chyuan Wang

发明人： Tsung-Yi Huang ,  Yuh-Chyuan Wang

IPC分类号： H01L21/8238

CPC分类号： H01L29/66659 ,  H01L21/266 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/7835

摘要： The present invention discloses a manufacturing method of a high voltage device. The high voltage device is formed in a first conductive type substrate. The high-voltage device includes: a second conductive type buried layer; a first conductive type high voltage well; and a second conductive type body. The high voltage well is formed by the same step for forming a first conductive type well or a first conductive type channel stop layer of a low voltage device formed in the same substrate. The body is formed by the same step for forming a second conductive type well of the low voltage device.

摘要翻译： 本发明公开了一种高压装置的制造方法。 高压器件形成在第一导电型衬底中。 高电压装置包括：第二导电型掩埋层; 第一导电型高压井; 和第二导电型体。 通过与形成在同一衬底中的低电压器件的第一导电型阱或第一导电型沟道阻挡层相同的步骤形成高电压阱。 主体由用于形成低压装置的第二导电型阱的相同步骤形成。