公开(公告)号：US07436707B2

公开(公告)日：2008-10-14

申请号：US11160693

申请日：2005-07-06

申请人： Chih-Wei Hung ,  Da Sung ,  Cheng-Yuan Hsu

发明人： Chih-Wei Hung ,  Da Sung ,  Cheng-Yuan Hsu

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： H01L29/66825 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/7885

摘要： A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.

摘要翻译： 闪存单元结构具有衬底，选择栅极，第一掺杂区域，浅第二掺杂区域，深第二掺杂区域和掺杂源极区域。 衬底具有堆叠栅极。 选择栅极形成在衬底上并且与堆叠栅极相邻。 第一离子形成区域在衬底中被掺杂并且与选择栅极相邻，作为漏极。 浅二次掺杂区形成在堆叠栅极下方的第一型掺杂区的一侧。 用作阱的深二次掺杂区形成在第一型掺杂区的下方，其中一侧与浅二次掺杂区接壤。 掺杂源区形成在浅二次掺杂区的一侧作为源。

公开(公告)号：US07335940B2

公开(公告)日：2008-02-26

申请号：US11307010

申请日：2006-01-19

申请人： I-Chun Chuang ,  Cheng-Yuan Hsu ,  Jui-Yu Pan

发明人： I-Chun Chuang ,  Cheng-Yuan Hsu ,  Jui-Yu Pan

IPC分类号： H01L29/788

CPC分类号： H01L29/7887 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

摘要： A method for manufacturing flash memory is provided. A tunneling dielectric layer, a conductive layer and a patterned mask layer that exposes a portion of the conductive layer are formed on a substrate. An oxide layer is formed on the exposed conductive layer so that the conductive layer is partitioned through the oxide layer into blocks. The oxide layer is removed and an inter-gate dielectric layer is formed in the opening. A control gate that completely fills the opening is formed. A cap layer is formed over the control gate. The mask layer is then removed. Using the cap layer as a mask, a portion of the conductive layer is removed to form two floating gates under the control gate. An insulating layer is formed on the substrate. Source/drain regions are formed in the substrate on the respective sides of the control gate.

摘要翻译： 提供一种制造闪存的方法。 在基板上形成有隧道电介质层，导电层和露出导电层的一部分的图案化掩模层。 在暴露的导电层上形成氧化物层，使得导电层通过氧化物层分隔成块。 去除氧化物层，并在开口中形成栅极间电介质层。 形成完全填充开口的控制门。 盖层形成在控制栅上。 然后去除掩模层。 使用盖层作为掩模，去除导电层的一部分以在控制栅极下方形成两个浮栅。 在基板上形成绝缘层。 源极/漏极区域形成在控制栅极的相应侧上的衬底中。

公开(公告)号：US20070133306A1

公开(公告)日：2007-06-14

申请号：US11308018

申请日：2006-03-03

申请人： Kuo-Tung Wang ,  Yen-Lee Pan ,  Kuo-Hao Chu ,  Cheng-Yuan Hsu

发明人： Kuo-Tung Wang ,  Yen-Lee Pan ,  Kuo-Hao Chu ,  Cheng-Yuan Hsu

IPC分类号： G11C16/04

CPC分类号： G11C16/16

摘要： An erasing method for a non-volatile memory is provided. The method includes the following two major steps. (a) A first voltage is applied to the odd-numbered select gates of each memory row and a second voltage is applied to the even-numbered select gates of each memory row such that the voltage difference between the first voltage and the second voltage is large enough for the electrons injected into the floating gate of the memory cells to be removed via the select gate. (b) A switchover operation is performed so that the first voltage is applied to the even-numbered select gates of each memory row and the second voltage is applied to the odd-numbered select gates of each memory row such that the electrons injected into the floating gates of the memory cells are pulled away via the select gates to turn the memory cells into an erased state.

摘要翻译： 提供了一种用于非易失性存储器的擦除方法。 该方法包括以下两个主要步骤。 （a）将第一电压施加到每个存储行的奇数选择栅极，并且将第二电压施加到每个存储行的偶数选择栅极，使得第一电压和第二电压之间的电压差为 足够大的注入到存储器单元的浮动栅极的电子通过选择栅极去除。 （b）执行切换操作，使得第一电压被施加到每个存储器行的偶数选择栅极，并且第二电压被施加到每个存储器行的奇数选择栅极，使得注入到 存储单元的浮动栅极经由选择栅极被拉开，以将存储单元转换成擦除状态。

公开(公告)号：US07180128B2

公开(公告)日：2007-02-20

申请号：US10904478

申请日：2004-11-12

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

IPC分类号： H01L21/331

CPC分类号： H01L21/28273 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7923

摘要： A non-volatile memory is provided. A plurality of stacked gate structure is formed on the substrate. The stacked gate structure includes, upward from the substrate surface, a select gate dielectric layer, a select gate and a cap layer. The spacers are disposed on the sidewalls of the stacked gate structures. The control gates are disposed over the substrate filling the space between the stacked gate structures and are mutually connected together. The floating gates are disposed between the stacked gate structures and positioned between the control gate and the substrate. The inter-gate dielectric layers are disposed between the control gates and the floating gates. The tunneling dielectric layers are disposed between the floating gates and the substrate. The source/drain regions are disposed in the substrate outside the two outermost stacked gate structures.

摘要翻译： 提供非易失性存储器。 在基板上形成多个堆叠的栅极结构。 堆叠的栅极结构包括从衬底表面向上的选择栅极电介质层，选择栅极和覆盖层。 间隔件设置在堆叠的栅极结构的侧壁上。 控制栅极设置在填充层叠栅极结构之间的空间的衬底上，并且彼此连接在一起。 浮置栅极位于堆叠的栅极结构之间并且位于控制栅极和衬底之间。 栅极间电介质层设置在控制栅极和浮栅之间。 隧道电介质层设置在浮置栅极和衬底之间。 源极/漏极区域设置在两个最外层叠的栅极结构之外的衬底中。

公开(公告)号：US20060175654A1

公开(公告)日：2006-08-10

申请号：US11161994

申请日：2005-08-25

申请人： Jui-Yu Pan ,  Cheng-Yuan Hsu ,  I-Chun Chuang ,  Chih-Wei Hung

发明人： Jui-Yu Pan ,  Cheng-Yuan Hsu ,  I-Chun Chuang ,  Chih-Wei Hung

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7782

摘要： A method for fabricating a flash memory is described. A mask layer having openings to expose a portion of the substrate is formed on the substrate. A tunneling dielectric layer is formed at the bottom surface of the openings. Conductive spacers are formed on the sidewalls of the openings. The conductive spacers are patterned to form a plurality of floating gates. A plurality of buried doped regions is formed in the substrate under the bottom surface of the openings. An inter-gate dielectric layer is formed over the substrate. A plurality of control gates is formed over the substrate to fill the openings. The mask layer is removed to form a plurality of memory units. A plurality of source regions and drain regions are formed in the substrate beside the memory units.

摘要翻译： 描述了一种用于制造闪速存储器的方法。 在基板上形成具有露出基板的一部分的开口的掩模层。 在开口的底表面处形成隧道电介质层。 导电间隔件形成在开口的侧壁上。 将导电间隔物图案化以形成多个浮动栅极。 在开口底面下方的基板中形成多个掩埋掺杂区域。 栅极间电介质层形成在衬底上。 多个控制栅极形成在衬底上以填充开口。 去除掩模层以形成多个存储单元。 在存储单元旁边的基板中形成多个源极区域和漏极区域。

公开(公告)号：US07005699B2

公开(公告)日：2006-02-28

申请号：US10707826

申请日：2004-01-15

申请人： Shih-Chang Chen ,  Cheng-Yuan Hsu ,  Chih-Wei Hung

发明人： Shih-Chang Chen ,  Cheng-Yuan Hsu ,  Chih-Wei Hung

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328

摘要： A NAND flash memory cell row includes first and second stacked gate structures, control and floating gates, intergate dielectric layer, tunnel oxide layer, doping regions and source/drain regions. The first stacked gate structures has an erase gate dielectric layer, an erase gate and a first cap layer. The second stacked gate structure has a select gate dielectric layer, a select gate and a second cap layer. The control gate is between each of the first stacked gate structures, and between each of the second stacked gate structures and adjacent first stacked gate structure. The floating gate is between the control gate and substrate. The inter-gate dielectric layer is between the control and floating gates. The tunnel oxide is between the floating gate and substrate. The doping regions are under the first stacked gate structure, and the source/drain regions are in the exposed substrate.

摘要翻译： NAND闪存单元行包括第一和第二堆叠栅极结构，控制和浮置栅极，栅极间介电层，隧道氧化物层，掺杂区域和源极/漏极区域。 第一层叠栅极结构具有擦除栅极电介质层，擦除栅极和第一覆盖层。 第二堆叠栅极结构具有选择栅极介电层，选择栅极和第二覆盖层。 控制栅极位于每个第一层叠栅极结构之间，并且在第二层叠栅极结构中的每一个和相邻的第一层叠栅极结构之间。 浮栅位于控制栅和基板之间。 栅极间介电层位于控制栅极和浮栅之间。 隧道氧化物位于浮栅和衬底之间。 掺杂区域处于第一堆叠栅极结构之下，并且源极/漏极区域处于暴露的衬底中。

公开(公告)号：US20050087892A1

公开(公告)日：2005-04-28

申请号：US10709125

申请日：2004-04-15

申请人： Cheng-Yuan Hsu ,  Chih-Wei Hung ,  Da Sung ,  Min-San Huang

发明人： Cheng-Yuan Hsu ,  Chih-Wei Hung ,  Da Sung ,  Min-San Huang

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115

CPC分类号： H01L27/11521 ,  G11C16/0483 ,  H01L27/115

摘要： A NAND flash memory cell array including a plurality of memory cell row is provided. Each of memory cell row includes a plurality of memory cells disposed between first selecting transistor and second selecting transistor connected in series. Each memory cell has a tunneling dielectric layer, a floating gate, an inter-gate dielectric, a control gate and source/drain regions. An erase gate is disposed between two adjacent memory cells. A plurality of word lines serve to connect the memory cells in rows. A source line serves to connect the source region of the first transistor in a row, whereas a plurality of bit lines serve to connect the drain region of second transistor in a row. A first selecting gate line and a second selecting gate line serve to connect the gate of the first transistor in a row and the gate of second transistor in a row respectively. A plurality of erase gate lines is connected to the erase gates in a row.

摘要翻译： 提供包括多个存储单元行的NAND快闪存储单元阵列。 每个存储单元行包括设置在串联连接的第一选择晶体管和第二选择晶体管之间的多个存储单元。 每个存储单元具有隧道介电层，浮栅，栅极间电介质，控制栅极和源/漏区。 擦除栅极设置在两个相邻的存储单元之间。 多个字线用于以行的形式连接存储器单元。 源极线用于将第一晶体管的源极区域连接成一行，而多个位线用于将第二晶体管的漏极区域连接成一行。 第一选择栅极线和第二选择栅极线用于分别连接一行中的第一晶体管的栅极和第二晶体管的栅极。 多条擦除栅极线一行连接到擦除栅极。

公开(公告)号：US06875660B2

公开(公告)日：2005-04-05

申请号：US10248867

申请日：2003-02-26

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of manufacturing a flash memory is provided. First, a substrate with a first gate structure and a second gate structure thereon is provided. The first gate structure and the second gate structure each comprises of a dielectric layer, a first conductive layer and a cap layer. A tunneling oxide layer is formed over the substrate and then a first spacer is formed on the sidewall of the first conductive layer. Thereafter, a second conductive layer is formed on one side designated for forming a source region of the sidewalls of the first gate structure and the second gate structure. Then, the source region is formed in the substrate in the designated area. Next, an inter-gate dielectric layer is formed over the second conductive layer and then an insulating layer is formed over the source region. After forming a third conductive layer over the area between the first gate structure and the second gate structure, a drain region is formed in the substrate.

摘要翻译： 提供一种制造闪速存储器的方法。 首先，提供其上具有第一栅极结构和第二栅极结构的衬底。 第一栅极结构和第二栅极结构各自包括介电层，第一导电层和盖层。 在衬底上形成隧道氧化物层，然后在第一导电层的侧壁上形成第一间隔物。 此后，在指定用于形成第一栅极结构和第二栅极结构的侧壁的源极区域的一侧上形成第二导电层。 然后，在指定区域中的基板中形成源极区域。 接下来，在第二导电层上形成栅极间电介质层，然后在源极区域上形成绝缘层。 在第一栅极结构和第二栅极结构之间的区域上形成第三导电层之后，在衬底中形成漏极区。

公开(公告)号：US06794710B2

公开(公告)日：2004-09-21

申请号：US10064883

申请日：2002-08-27

申请人： Ko-Hsing Chang ,  Cheng-Yuan Hsu

发明人： Ko-Hsing Chang ,  Cheng-Yuan Hsu

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7883

摘要： A split-gate flash memory structure. The flash memory at least includes a substrate having a trench therein, a floating gate, a select gate and a source/drain region. The floating gate is formed inside the trench such that the upper surface of the floating gate is below the substrate surface. The select gate is also formed inside the trench above the floating gate such that the select gate protrudes beyond the substrate surface. The source/drain region is formed in the substrate on each side of the select gate. The source/drain region and the floating gate are separated from each other by a distance. A tunnel oxide layer separates the floating gate from the substrate and a gate dielectric layer separates the floating gate from the select gate. A dielectric layer separates the select gate from the substrate.

摘要翻译： 分闸式闪存结构。 闪存至少包括其中具有沟槽的衬底，浮置栅极，选择栅极和源极/漏极区域。 浮动栅极形成在沟槽内，使得浮动栅极的上表面在衬底表面下方。 选择栅极也形成在浮置栅极上方的沟槽内，使得选择栅极突出超过衬底表面。 源极/漏极区域形成在选择栅极的每一侧上的衬底中。 源极/漏极区域和浮置栅极彼此间隔一定距离。 隧道氧化层将浮置栅极与衬底分开，并且栅极电介质层将浮动栅极与选择栅极分离。 电介质层将选择栅极与衬底分开。

公开(公告)号：US20120261736A1

公开(公告)日：2012-10-18

申请号：US13175896

申请日：2011-07-04

申请人： Cheng-Yuan Hsu ,  Chun-Hsiao Li

发明人： Cheng-Yuan Hsu ,  Chun-Hsiao Li

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/11521

摘要： A non-volatile memory device includes a substrate, a gate stack, a selecting gate, an erasing gate, a source region, and a drain region. The gate stack on the substrate includes from bottom to top a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a spacer that is located between sidewalls of the control gate and the inter-gate dielectric layer. A side of the floating gate adjacent to the erasing gate has a warp-around profile and a sharp corner protruding from a vertical surface of the spacer. The selecting and erasing gates are respectively located at first and second sides of the substrate of the gate stack. The source region is located in the substrate under the erasing gate. The drain region is located in the substrate at a side of the selecting gate.

摘要翻译： 非易失性存储器件包括衬底，栅极堆叠，选择栅极，擦除栅极，源极区域和漏极区域。 衬底上的栅极堆叠包括从底部到顶部的隧道介电层，浮栅，栅极间介质层，控制栅极和间隔物，其位于控制栅极和栅极间介电层的侧壁之间 。 与擦除栅极相邻的浮动栅极的一侧具有翘曲轮廓和从间隔件的垂直表面突出的尖角。 选择和擦除栅极分别位于栅极堆叠的衬底的第一和第二侧。 源极区域位于擦除栅极下方的衬底中。 漏极区位于选择栅极侧的衬底中。