公开(公告)号：US08686504B2

公开(公告)日：2014-04-01

申请号：US13555163

申请日：2012-07-22

申请人： Tsung-Yi Huang ,  Chien-Hao Huang

发明人： Tsung-Yi Huang ,  Chien-Hao Huang

IPC分类号： H01L29/66

CPC分类号： H01L29/78 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816

摘要： The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively.

公开(公告)号：US08643136B2

公开(公告)日：2014-02-04

申请号：US13037678

申请日：2011-03-01

申请人： Tsung-Yi Huang ,  Kuo-Hsuan Lo

发明人： Tsung-Yi Huang ,  Kuo-Hsuan Lo

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/66681 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/7835

摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate in which isolation regions are formed for defining a device region; a gate formed on the first conductive type substrate; a source and a drain formed in the device region and located at both sides of the gate respectively, and doped with second conductive type impurities; a second conductive type well, which is formed in the first conductive type substrate, and surrounds the drain from top view; and a first deep trench isolation structure, which is formed in the first conductive type substrate, and is located in the second conductive type well between the source and the drain from top view, wherein the depth of the first deep trench isolation structure is deeper than the second conductive type well from the cross-sectional view.

摘要翻译： 本发明公开了一种高压器件及其制造方法。 高压器件包括：第一导电型衬底，其中形成隔离区以限定器件区域; 形成在所述第一导电型基板上的栅极; 在器件区域中分别形成并位于栅极两侧的源极和漏极，并掺杂有第二导电类型杂质; 第二导电型阱，其形成在第一导电类型基板中，并且从俯视图围绕漏极; 以及第一深沟槽隔离结构，其形成在第一导电类型基板中，并且从顶视图位于源极和漏极之间的第二导电类型阱中，其中第一深沟槽隔离结构的深度比 第二导电类型井从横截面图。

公开(公告)号：US20130299840A1

公开(公告)日：2013-11-14

申请号：US13466550

申请日：2012-05-08

申请人： Chieh-Hsiung Kuan ,  Ting-Wei Liao ,  Chien-Wei Chiu ,  Tsung-Yi Huang

发明人： Chieh-Hsiung Kuan ,  Ting-Wei Liao ,  Chien-Wei Chiu ,  Tsung-Yi Huang

IPC分类号： H01L29/20 ,  H01L21/28 ,  H01L29/872

CPC分类号： H01L29/417 ,  H01L29/2003 ,  H01L29/413 ,  H01L29/66212 ,  H01L29/872

摘要： The present invention discloses a Schottky barrier diode (SBD) and a manufacturing method thereof. The SBD includes: a semiconductor layer, which has multiple openings forming an opening array; and an anode, which has multiple conductive protrusions protruding into the multiple openings and forming a conductive array; wherein a Schottky contact is formed between the semiconductor layer and the anode.

摘要翻译： 本发明公开了一种肖特基势垒二极管（SBD）及其制造方法。 SBD包括：半导体层，其具有形成开口阵列的多个开口; 以及阳极，其具有突出到所述多个开口中并形成导电阵列的多个导电突起; 其中在所述半导体层和所述阳极之间形成肖特基接触。

公开(公告)号：US20130045577A1

公开(公告)日：2013-02-21

申请号：US13317568

申请日：2011-10-21

申请人： Tsung-Yi Huang ,  Yuh-Chyuan Wang

发明人： Tsung-Yi Huang ,  Yuh-Chyuan Wang

IPC分类号： H01L21/8238

CPC分类号： H01L29/66659 ,  H01L21/266 ,  H01L21/82385 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/7835

摘要： The present invention discloses a manufacturing method of a high voltage device. The high voltage device is formed in a first conductive type substrate. The high-voltage device includes: a second conductive type buried layer; a first conductive type high voltage well; and a second conductive type body. The high voltage well is formed by the same step for forming a first conductive type well or a first conductive type channel stop layer of a low voltage device formed in the same substrate. The body is formed by the same step for forming a second conductive type well of the low voltage device.

摘要翻译： 本发明公开了一种高压装置的制造方法。 高压器件形成在第一导电型衬底中。 高电压装置包括：第二导电型掩埋层; 第一导电型高压井; 和第二导电型体。 通过与形成在同一衬底中的低电压器件的第一导电型阱或第一导电型沟道阻挡层相同的步骤形成高电压阱。 主体由用于形成低压装置的第二导电型阱的相同步骤形成。

公开(公告)号：US20120319202A1

公开(公告)日：2012-12-20

申请号：US13161072

申请日：2011-06-15

申请人： Tsung-Yi Huang ,  Huan-Ping Chu

发明人： Tsung-Yi Huang ,  Huan-Ping Chu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/66659

摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate having a device region; a gate, which is located on a surface of the substrate; a second conductive type source and a second conductive type drain in the device region at different sides of the gate respectively; and a second conductive type drift region, which is located in the device region, between the source and the drain. The gate includes: a conductive layer for receiving a gate voltage; and multiple dielectric layers with different thicknesses, located at different horizontal positions. From cross-section view, each dielectric layer is between the conductive layer and the substrate, and the multiple dielectric layers are arranged in an order from thinner to thicker from a side closer to the source to a side closer to the drain.

摘要翻译： 本发明公开了一种高压器件及其制造方法。 高电压装置包括：具有器件区域的第一导电型衬底; 位于所述基板的表面上的栅极; 在栅极的不同侧的器件区域中的第二导电类型源极和第二导电类型漏极; 以及位于源极和漏极之间的器件区域中的第二导电类型漂移区。 栅极包括：用于接收栅极电压的导电层; 和具有不同厚度的多个电介质层，位于不同的水平位置。 从横截面图，每个电介质层位于导电层和衬底之间，并且多个电介质层从更靠近源的一侧到靠近漏极的一侧以从更薄到较厚的顺序排列。

公开(公告)号：US20120217579A1

公开(公告)日：2012-08-30

申请号：US13136703

申请日：2011-08-08

申请人： Tsung-Yi Huang ,  Ying-Shiou Lin

发明人： Tsung-Yi Huang ,  Ying-Shiou Lin

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/7835

摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having a P (or N) type well and an isolation structure for defining a device region; a drift region, located in the device region, having a first region and a second region wherein the first region is an N (or P) type region, and the second region is a P (or N) type region or an N (or P) type region with different dopant concentration from the first region, and from top view, the first region and the second region include sub-regions distributed in the drift region; an N (or P) type source and drain; and a gate on a surface of the substrate, between the source and drain in the device region.

摘要翻译： 本发明公开了一种高压器件及其制造方法。 高压装置包括：具有P（或N）型阱的衬底和用于限定器件区域的隔离结构; 位于器件区域中的漂移区域具有第一区域和第二区域，其中第一区域是N（或P）型区域，第二区域是P（或N）型区域或N（或 P）型区域，并且从顶视图看，第一区域和第二区域包括分布在漂移区域中的子区域; N（或P）型源极和漏极; 以及衬底的表面上的栅极，位于器件区域中的源极和漏极之间。

公开(公告)号：US20120187483A1

公开(公告)日：2012-07-26

申请号：US13066622

申请日：2011-04-20

申请人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Ching-Yao Yang ,  Tsung-Yi Huang ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L29/78 ,  H01L21/8232 ,  H01L21/336

CPC分类号： H01L29/4238 ,  H01L21/28114 ,  H01L21/823425 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: an isolation structure for defining device regions; a gate with a ring-shaped structure; a drain located outside the ring; and a lightly doped drain, a source, and a body electrode located inside the ring. To increase the sub-threshold voltage at the corners of the gate, the corners are located completely on the isolation structure, or the lightly doped drain is apart from the corners by a predetermined distance.

摘要翻译： 本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS设备包括：用于定义设备区域的隔离结构; 具有环形结构的门; 位于环外的排水沟; 以及位于环内的轻掺杂漏极，源极和体电极。 为了增加栅极角落处的次阈值电压，角部完全位于隔离结构上，或者轻掺杂漏极与角分开预定距离。

公开(公告)号：US20120161235A1

公开(公告)日：2012-06-28

申请号：US13317323

申请日：2011-10-15

申请人： Tsung-Yi Huang ,  Jin-Lian Su

发明人： Tsung-Yi Huang ,  Jin-Lian Su

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/41758 ,  H01L27/0277 ,  H01L29/6659 ,  H01L29/7835

摘要： The present invention discloses an electrostatic discharge protection device and a manufacturing method thereof. The electrostatic discharge protection device includes: a substrate, a gate, two N type lightly doped drains, an N type source, an N type drain, and two N type doped regions extending downward beneath and in contact with the source and drain respectively, such that when the source and drain are conducted with each other, at least part of the current flows through the two downwardly extending doped regions to increase the electrostatic discharge protection voltage of the electrostatic discharge protection device.

摘要翻译： 本发明公开了一种静电放电保护装置及其制造方法。 静电放电保护装置包括：基板，栅极，两个N型轻掺杂漏极，N型源极，N型漏极和分别向下延伸并与源极和漏极接触的两个N型掺杂区域， 当源极和漏极彼此导通时，至少部分电流流过两个向下延伸的掺杂区域以增加静电放电保护器件的静电放电保护电压。

公开(公告)号：US08183626B2

公开(公告)日：2012-05-22

申请号：US13027097

申请日：2011-02-14

申请人： Chen-Liang Chu ,  Chun-Ting Liao ,  Tsung-Yi Huang ,  Fei-Yuh Chen

发明人： Chen-Liang Chu ,  Chun-Ting Liao ,  Tsung-Yi Huang ,  Fei-Yuh Chen

IPC分类号： H01L27/06

CPC分类号： H01L29/7833 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7835

摘要： An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.

摘要翻译： 集成电路结构包括半导体衬底中的高电压阱（HVW）区域; HVW区域中的第一双扩散（DD）区域; 和HVW区域中的第二DD区域。 第一DD区域和第二DD区域通过HVW区域的中间部分彼此间隔开。 凹部从半导体衬底的顶表面延伸到HVW区域和第二DD区域的中间部分。 栅极电介质延伸到凹部中并覆盖凹部的底部。 栅极电极在栅极电介质上方。 第一源/漏区在第一DD区。 第二个源极/漏极区域位于第二个DD区域。

公开(公告)号：US08143130B1

公开(公告)日：2012-03-27

申请号：US12910051

申请日：2010-10-22

申请人： Tsung-Yi Huang

发明人： Tsung-Yi Huang

IPC分类号： H01L21/8236

CPC分类号： H01L27/0883 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462

摘要： The present invention discloses a method of manufacturing a depletion metal oxide semiconductor (MOS) device. The method includes: providing a substrate; forming a first conductive type well and an isolation region in the substrate to define a device area; defining a drift region, a source, a drain, and a threshold voltage adjustment region, and implanting second conductive type impurities to form the drift region, the source, the drain, and the threshold voltage adjustment region, respectively; defining a breakdown protection region between the drain and the threshold voltage adjustment region, and implanting first conductive type impurities to form the breakdown protection region; and forming a gate in the device area; wherein a part of the breakdown protection region is below the gate, and the breakdown protection region covers an edge of the threshold voltage adjustment region.

摘要翻译： 本发明公开了一种制造耗尽金属氧化物半导体（MOS）器件的方法。 该方法包括：提供衬底; 在衬底中形成第一导电类型阱和隔离区以限定器件区域; 限定漂移区域，源极，漏极和阈值电压调整区域，以及分别植入第二导电类型杂质以形成漂移区域，源极，漏极和阈值电压调整区域; 限定漏极和阈值电压调整区域之间的击穿保护区域，以及注入第一导电型杂质以形成击穿保护区域; 以及在所述设备区域中形成栅极; 其中所述击穿保护区域的一部分在所述栅极下方，所述击穿保护区域覆盖所述阈值电压调整区域的边缘。