公开(公告)号：US20070047300A1

公开(公告)日：2007-03-01

申请号：US11474430

申请日：2006-06-26

申请人： Doo-Sub Lee ,  Heung-Soo Lim

发明人： Doo-Sub Lee ,  Heung-Soo Lim

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C11/5642

摘要： A flash memory device comprises an array of memory cells arranged in rows and columns and a word line voltage generating circuit adapted to generate a plurality of read voltages at the same time during a multi-bit read operation. The device further comprises a row selecting circuit adapted to select one of the rows and drive the selected row with a word line voltage, and voltage lines transmitting the respective read voltages to the row selecting circuit as the word line voltage. The read voltages are supplied to the respective voltage lines before starting read periods of the multi-bit read operation.

摘要翻译： 闪速存储器件包括排列成行和列的存储单元的阵列和适于在多位读取操作期间同时产生多个读取电压的字线电压产生电路。 该装置还包括行选择电路，其适于选择一行中的一行并用字线电压驱动所选择的行，以及电压线将各个读电压传送到行选择电路作为字线电压。 在开始多位读取操作的读取周期之前，读取电压被提供给各个电压线。

公开(公告)号：US07405977B2

公开(公告)日：2008-07-29

申请号：US11474430

申请日：2006-06-26

申请人： Doo-Sub Lee ,  Heung-Soo Lim

发明人： Doo-Sub Lee ,  Heung-Soo Lim

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/26 ,  G11C11/5642

摘要： A flash memory device comprises an array of memory cells arranged in rows and columns and a word line voltage generating circuit adapted to generate a plurality of read voltages at the same time during a multi-bit read operation. The device further comprises a row selecting circuit adapted to select one of the rows and drive the selected row with a word line voltage, and voltage lines transmitting the respective read voltages to the row selecting circuit as the word line voltage. The read voltages are supplied to the respective voltage lines before starting read periods of the multi-bit read operation.

摘要翻译： 闪速存储器件包括排列成行和列的存储单元的阵列和适于在多位读取操作期间同时产生多个读取电压的字线电压产生电路。 该装置还包括行选择电路，其适于选择一行中的一行并用字线电压驱动所选择的行，以及电压线将各个读电压传送到行选择电路作为字线电压。 在开始多位读取操作的读取周期之前，读取电压被提供给各个电压线。

公开(公告)号：US07286413B2

公开(公告)日：2007-10-23

申请号：US11257074

申请日：2005-10-25

申请人： Jae-Yong Jeong ,  Heung-Soo Lim

发明人： Jae-Yong Jeong ,  Heung-Soo Lim

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C16/24

摘要： Disclosed are a non-volatile memory device and a method of programming the same. The method comprises applying a wordline voltage, a bitline voltage, and a bulk voltage to a memory cell during a plurality of program loops. In cases where the bitline voltage falls below a first predetermined detection voltage during a current program loop, or the bulk voltage becomes higher than a second predetermined detection voltage, the same wordline voltage is used in the current programming loop and a next program loop following the current program loop. Otherwise, the wordline voltage is incremented by a predetermined amount before the next programming loop.

摘要翻译： 公开了一种非易失性存储器件及其编程方法。 该方法包括在多个程序循环期间将字线电压，位线电压和体电压施加到存储器单元。 在当前程序循环期间位线电压下降到低于第一预定检测电压或体电压变得高于第二预定检测电压的情况下，在当前编程环路中使用相同的字线电压，并在下一个程序循环 当前程序循环。 否则，在下一个编程循环之前，字线电压增加预定量。

公开(公告)号：US20070109873A1

公开(公告)日：2007-05-17

申请号：US11649815

申请日：2007-01-05

申请人： Jae-Yong Jeong ,  Heung-Soo Lim

发明人： Jae-Yong Jeong ,  Heung-Soo Lim

IPC分类号： G11C7/10

CPC分类号： G11C16/30 ,  G11C16/10

摘要： Disclosed is a non-volatile memory device and a method of programming the same. The non-volatile memory device is programmed by applying a wordline voltage, a bitline voltage, and a bulk voltage to memory cells within the device. During a programming operation for the device, the bulk voltage is generated by a first pump. However, where the bulk voltage exceeds a predetermined detection voltage, a second pump is further activated in order to lower the bulk voltage.

摘要翻译： 公开了一种非易失性存储器件及其编程方法。 通过将字线电压，位线电压和体电压施加到器件内的存储器单元来编程非易失性存储器件。 在器件的编程操作期间，体电压由第一泵产生。 然而，在体电压超过预定检测电压的情况下，第二泵进一步被激活以便降低体电压。

公开(公告)号：US07130240B2

公开(公告)日：2006-10-31

申请号：US10822167

申请日：2004-04-08

申请人： Dong-Hyuk Chae ,  Heung-Soo Lim

发明人： Dong-Hyuk Chae ,  Heung-Soo Lim

IPC分类号： G11C8/00

CPC分类号： G11C16/16

摘要： A semiconductor memory device is operable with a multi-sector erase mode for a multiplicity of memory chips, including a cell array, a register circuit containing information for a sector to be erased, an address clock driving circuit for contemporaneously generating an address clock signal from each memory chips, a counter for generating address signals in sequence, a core driver for executing an erase operation for the sector, and a control circuit thereof.

摘要翻译： 半导体存储器件可用于多扇区擦除模式，用于多个存储器芯片，包括单元阵列，包含用于要擦除的扇区的信息的寄存器电路，用于同时产生地址时钟信号的地址时钟驱动电路， 每个存储器芯片，用于依次产生地址信号的计数器，用于执行扇区的擦除操作的核心驱动器及其控制电路。

公开(公告)号：US07742341B2

公开(公告)日：2010-06-22

申请号：US12190215

申请日：2008-08-12

申请人： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Im

发明人： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Im

IPC分类号： G11C16/06

CPC分类号： G11C16/12 ,  G11C16/3454

摘要： A NOR flash memory device and related programming method are disclosed. The programming method includes programming data in a memory cell and, during a program verification operation, controlling the supply of current from a sense amplifier to the memory cell in relation to the value of the programmed data. Wherein a program verification operation is indicated, current is provided from the sense amplifier to the memory cell. Where a program verification operation is not indicated, current is cut off from the sense amplifier.

摘要翻译： 公开了一种NOR闪存器件及相关编程方法。 编程方法包括在存储器单元中编程数据，并且在程序验证操作期间，相对于编程数据的值控制从读出放大器到存储单元的电流供应。 其中指示程序验证操作，从读出放大器向存储单元提供电流。 在没有指示程序验证操作的情况下，从感测放大器切断电流。

公开(公告)号：US07457165B2

公开(公告)日：2008-11-25

申请号：US11855531

申请日：2007-09-14

申请人： Jae-Yong Jeong ,  Heung-Soo Lim

发明人： Jae-Yong Jeong ,  Heung-Soo Lim

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C16/24

摘要： Disclosed are a non-volatile memory device and a method of programming the same. The method comprises applying a wordline voltage, a bitline voltage, and a bulk voltage to a memory cell during a plurality of program loops. In cases where the bitline voltage falls below a first predetermined detection voltage during a current program loop, or the bulk voltage becomes higher than a second predetermined detection voltage, the same wordline voltage is used in the current programming loop and a next program loop following the current program loop. Otherwise, the wordline voltage is incremented by a predetermined amount before the next programming loop.

摘要翻译： 公开了一种非易失性存储器件及其编程方法。 该方法包括在多个程序循环期间将字线电压，位线电压和体电压施加到存储器单元。 在当前程序循环期间位线电压下降到低于第一预定检测电压或体电压变得高于第二预定检测电压的情况下，在当前编程环路中使用相同的字线电压，并在下一个程序循环 当前程序循环。 否则，在下一个编程循环之前，字线电压增加预定量。

公开(公告)号：US20070047320A1

公开(公告)日：2007-03-01

申请号：US11486227

申请日：2006-07-13

申请人： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Lim

发明人： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Lim

IPC分类号： G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： A program operation for a NOR flash memory device is verified by programming data in a memory cell, performing a dummy verify operation on the memory cell, and performing a program verify operation on the memory cell based on a result of the dummy verify operation.

摘要翻译： 通过在存储器单元中编程数据，对存储单元执行虚拟验证操作，并且基于虚拟验证操作的结果对存储器单元执行程序验证操作来验证NOR闪速存储器件的编程操作。

公开(公告)号：US20070025158A1

公开(公告)日：2007-02-01

申请号：US11407969

申请日：2006-04-21

申请人： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Im

发明人： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Im

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/12 ,  G11C16/3454

摘要： A NOR flash memory device and related programming method are disclosed. The programming method includes programming data in a memory cell and, during a program verification operation, controlling the supply of current from a sense amplifier to the memory cell in relation to the value of the programmed data. Wherein a program verification operation is indicated, current is provided from the sense amplifier to the memory cell. Where a program verification operation is not indicated, current is cut off from the sense amplifier.

摘要翻译： 公开了一种NOR闪存器件及相关编程方法。 编程方法包括在存储器单元中编程数据，并且在程序验证操作期间，相对于编程数据的值控制从读出放大器到存储单元的电流供应。 其中指示程序验证操作，从读出放大器向存储单元提供电流。 在没有指示程序验证操作的情况下，从感测放大器切断电流。

公开(公告)号：US07426143B2

公开(公告)日：2008-09-16

申请号：US11407969

申请日：2006-04-21

申请人： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Im

发明人： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Im

IPC分类号： G11C11/34 ,  G11C16/06

CPC分类号： G11C16/12 ,  G11C16/3454

摘要： A NOR flash memory device and related programming method are disclosed. The programming method includes programming data in a memory cell and, during a program verification operation, controlling the supply of current from a sense amplifier to the memory cell in relation to the value of the programmed data. Wherein a program verification operation is indicated, current is provided from the sense amplifier to the memory cell. Where a program verification operation is not indicated, current is cut off from the sense amplifier.

摘要翻译： 公开了一种NOR闪存器件及相关编程方法。 编程方法包括在存储器单元中编程数据，并且在程序验证操作期间，相对于编程数据的值控制从读出放大器到存储单元的电流供应。 其中指示程序验证操作，从读出放大器向存储单元提供电流。 在没有指示程序验证操作的情况下，从感测放大器切断电流。