公开(公告)号：US08116132B2

公开(公告)日：2012-02-14

申请号：US12348348

申请日：2009-01-05

Applicant: Jae-woo Im

Inventor： Jae-woo Im

IPC: G11C11/34

CPC classification number: G11C5/145 ,  G11C8/10 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/30

Abstract: Provided is a flash memory device including a wordline voltage generating unit, a switch unit, a row decoder and a control circuit. The wordline voltage generating unit generates at least one wordline voltage for read operations of a multi-level cell in the flash memory device. The switch unit receives the at least one wordline voltage and an initialization voltage, and selectively outputs the at least one wordline voltage and the initialization voltage through a switching operation. The row decoder operates the wordline of the multi-level cell based on an output of the switch unit. The control circuit provides at least one control signal to the switch unit, which outputs the initialization voltage in at least one section of the read operation in response to the at least one control signal.

Abstract translation: 提供了一种包括字线电压产生单元，开关单元，行解码器和控制电路的闪存器件。 字线电压产生单元产生用于闪存器件中的多电平单元的读取操作的至少一个字线电压。 开关单元接收至少一个字线电压和初始化电压，并且通过切换操作选择性地输出至少一个字线电压和初始化电压。 行解码器基于开关单元的输出来操作多电平单元的字线。 所述控制电路向所述开关单元提供至少一个控制信号，所述控制信号响应于所述至少一个控制信号在所述读取操作的至少一个部分中输出所述初始化电压。

公开(公告)号：US20090052253A1

公开(公告)日：2009-02-26

申请号：US12222635

申请日：2008-08-13

Applicant: Jae-woo Im

Inventor： Jae-woo Im

IPC: G11C16/06 ,  G11C8/00

CPC classification number: G11C8/12 ,  G11C8/14 ,  G11C16/30 ,  G11C2216/22

Abstract: Provided is a device and method for reducing a fluctuation of a read voltage generated during a read while write (RWW) operation. A semiconductor memory device may include a write voltage generator configured to generate a write voltage to perform the write operation to at least one of a plurality of banks where the write voltage generator generates the write voltage to have a voltage level of a read voltage before the write operation changes to a read operation. The semiconductor device may also include a read voltage generator configured to generate a read voltage to perform the read operation to at least one of the other plurality of banks and/or a plurality of switches configured to switch a voltage applied to at least one of the banks to one of the write voltage and the read voltage in response to a plurality of control signals.

Abstract translation: 提供了一种用于在写入（RWW）操作期间减少读取期间产生的读取电压的波动的装置和方法。 一种半导体存储器件可以包括：写入电压发生器，被配置为产生写入电压，以对写入电压发生器产生写入电压的多个存储体中的至少一个进行写入操作，以在其之前具有读取电压的电压电平 写操作更改为读操作。 半导体器件还可以包括读取电压发生器，其被配置为产生读取电压以对其他多个存储体中的至少一个存储体执行读取操作，和/或多个开关被配置为切换施加到至少一个存储器 响应于多个控制信号将其写入写入电压和读取电压之一。

公开(公告)号：US07426143B2

公开(公告)日：2008-09-16

申请号：US11407969

申请日：2006-04-21

Applicant: Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Im

Inventor： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Im

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G11C16/12 ,  G11C16/3454

Abstract: A NOR flash memory device and related programming method are disclosed. The programming method includes programming data in a memory cell and, during a program verification operation, controlling the supply of current from a sense amplifier to the memory cell in relation to the value of the programmed data. Wherein a program verification operation is indicated, current is provided from the sense amplifier to the memory cell. Where a program verification operation is not indicated, current is cut off from the sense amplifier.

Abstract translation: 公开了一种NOR闪存器件及相关编程方法。 编程方法包括在存储器单元中编程数据，并且在程序验证操作期间，相对于编程数据的值控制从读出放大器到存储单元的电流供应。 其中指示程序验证操作，从读出放大器向存储单元提供电流。 在没有指示程序验证操作的情况下，从感测放大器切断电流。

公开(公告)号：US08760919B2

公开(公告)日：2014-06-24

申请号：US13598892

申请日：2012-08-30

Applicant: Jung-Ho Song ,  Jin-Yub Lee ,  Jae-Woo Im ,  Seung-Jae Lee ,  Sang-So Park

Inventor： Jung-Ho Song ,  Jin-Yub Lee ,  Jae-Woo Im ,  Seung-Jae Lee ,  Sang-So Park

IPC: G11C11/56 ,  G11C16/04

CPC classification number: G11C11/56 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3404 ,  G11C2211/56

Abstract: A method is provided for reading data in a nonvolatile memory device. The method includes performing a first read operation on multiple multi-level memory cells (MLCs), performing a first sensing operation on at least one flag cell corresponding to the MLCs, selectively performing a second read operation on the MLCs based on a result of the first sensing operation, and performing a second sensing operation on the at least one flag cell when the second read operation is performed. Read data is output based on results of the first read operation and the first sensing operation when the second read operation is not performed, and the read data is output based on result of the first read operation, the first sensing operation, the second read operation and the second sensing operation when the second read operation is performed. The read data corresponds to programmed data in the MLCs.

Abstract translation: 提供了一种用于在非易失性存储器件中读取数据的方法。 该方法包括：对多个多电平存储器单元（MLC），在对应于MLC中的至少一个标志单元，基于所述结果选择性地执行上的MLC的第二读取操作执行第一读出操作的第一次读操作 第一感测操作，并且当执行第二读取操作时对所述至少一个标志单元执行第二感测操作。 在不执行第二读取操作时，基于第一读取操作和第一感测操作的结果输出读取数据，并且基于第一读取操作，第一感测操作，第二读取操作的结果来输出读取数据 以及执行第二读取操作时的第二感测操作。 读取数据对应于MLC中的编程数据。

公开(公告)号：US20120106251A1

公开(公告)日：2012-05-03

申请号：US13347800

申请日：2012-01-11

Applicant: Jae-woo IM

Inventor： Jae-woo IM

IPC: G11C16/04

CPC classification number: G11C5/145 ,  G11C8/10 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/30

Abstract: Provided is a flash memory device including a wordline voltage generating unit, a switch unit, a row decoder and a control circuit. The wordline voltage generating unit generates at least one wordline voltage for read operations of a multi-level cell in the flash memory device. The switch unit receives the at least one wordline voltage and an initialization voltage, and selectively outputs the at least one wordline voltage and the initialization voltage through a switching operation. The row decoder operates the wordline of the multi-level cell based on an output of the switch unit. The control circuit provides at least one control signal to the switch unit, which outputs the initialization voltage in at least one section of the read operation in response to the at least one control signal.

Abstract translation: 提供了一种包括字线电压产生单元，开关单元，行解码器和控制电路的闪存器件。 字线电压产生单元产生用于闪存器件中的多电平单元的读取操作的至少一个字线电压。 开关单元接收至少一个字线电压和初始化电压，并且通过切换操作选择性地输出至少一个字线电压和初始化电压。 行解码器基于开关单元的输出来操作多电平单元的字线。 所述控制电路向所述开关单元提供至少一个控制信号，所述控制信号响应于所述至少一个控制信号在所述读取操作的至少一个部分中输出所述初始化电压。

公开(公告)号：US07925820B2

公开(公告)日：2011-04-12

申请号：US11567162

申请日：2006-12-05

Applicant: Jae-Woo Im

Inventor： Jae-Woo Im

IPC: G06F12/00

CPC classification number: G11C16/10 ,  G11C2216/14

Abstract: A nonvolatile semiconductor memory device and a program method are provided in an embodiment. Data is scanned to search data bits to be selectively programmed. The searched data bits are simultaneously programmed according to a predetermined number. Since data scanning and programming are conducted using a pipeline processing, an average time required for programming data is effectively shortened.

Abstract translation: 在一个实施例中提供了非易失性半导体存储器件和编程方法。 扫描数据以搜索数据位以进行选择性编程。 搜索到的数据位根据预定数量同时编程。 由于使用流水线处理进行数据扫描和编程，因此有效地缩短了编程数据所需的平均时间。

公开(公告)号：US07843722B2

公开(公告)日：2010-11-30

申请号：US11765057

申请日：2007-06-19

Applicant: Jae-Woo Im

Inventor： Jae-Woo Im

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A nonvolatile semiconductor memory device and a programming method thereof are provided. The programming method includes first programming a cell among a plurality of adjacent memory cells to the highest threshold voltage distribution corresponding to a data state, and subsequently programming the other adjacent cells to the lower threshold voltage distributions corresponding to second and third data states. The second data state and the third data state may have the second highest threshold voltage distribution and the third highest threshold voltage distribution, respectively, or the third highest threshold voltage distribution and the second highest threshold voltage distribution, respectively.

Abstract translation: 提供了一种非易失性半导体存储器件及其编程方法。 编程方法包括首先将多个相邻存储器单元之间的单元编程为对应于数据状态的最高阈值电压分布，然后将其它相邻单元编程为对应于第二和第三数据状态的较低阈值电压分布。 第二数据状态和第三数据状态可以分别具有第二高阈值电压分布和第三高阈值电压分布，或者分别具有第三高阈值电压分布和第二高阈值电压分布。

公开(公告)号：US07742341B2

公开(公告)日：2010-06-22

申请号：US12190215

申请日：2008-08-12

Applicant: Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Im

Inventor： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Im

IPC: G11C16/06

CPC classification number: G11C16/12 ,  G11C16/3454

Abstract: A NOR flash memory device and related programming method are disclosed. The programming method includes programming data in a memory cell and, during a program verification operation, controlling the supply of current from a sense amplifier to the memory cell in relation to the value of the programmed data. Wherein a program verification operation is indicated, current is provided from the sense amplifier to the memory cell. Where a program verification operation is not indicated, current is cut off from the sense amplifier.

Abstract translation: 公开了一种NOR闪存器件及相关编程方法。 编程方法包括在存储器单元中编程数据，并且在程序验证操作期间，相对于编程数据的值控制从读出放大器到存储单元的电流供应。 其中指示程序验证操作，从读出放大器向存储单元提供电流。 在没有指示程序验证操作的情况下，从感测放大器切断电流。

公开(公告)号：US07190619B2

公开(公告)日：2007-03-13

申请号：US11206586

申请日：2005-08-17

Applicant: Jae-Woo Im

Inventor： Jae-Woo Im

IPC: G11C16/04

CPC classification number: G11C16/102

Abstract: A circuit for indicating termination of scan of bits to be programmed in a nonvolatile semiconductor memory device includes a counting unit, a set bit number provision unit and a comparison unit. The counting unit counts the predetermined number of bits to be programmed, and provides a group of counting bit signals indicating the number of bits to be programmed. The set bit number provision unit provides a group of set bit signals indicating the number of set bits. The number of set bits can be externally controlled. The comparison unit compares the group of counting bit signals with the group of set bit signals and ultimately provides a scan termination signal used to control programming for the memory array. The logic level of the scan termination signal is changed when the number of bits to be programmed attains the number of set bits. Accordingly, a designer or user of a nonvolatile semiconductor memory device can adjust the number of bits to be simultaneously programmed, and the time required for a complete program operation can be shortened.

Abstract translation: 用于指示在非易失性半导体存储器件中要编程的位的扫描结束的电路包括计数单元，设定位数提供单元和比较单元。 计数单元对要编程的预定位数进行计数，并提供指示要编程的位数的一组计数位信号。 设置位数提供单元提供指示设置位数的一组置位信号。 设置位的数量可以从外部控制。 比较单元将一组计数位信号与置位位信号组进行比较，最终提供用于控制存储器阵列编程的扫描终止信号。 当待编程的位数达到设定位数时，扫描终止信号的逻辑电平就会改变。 因此，非易失性半导体存储器件的设计者或用户可以调节要同时编程的位数，并且可以缩短完成程序操作所需的时间。

公开(公告)号：US20070025158A1

公开(公告)日：2007-02-01

申请号：US11407969

申请日：2006-04-21

Applicant: Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Im

Inventor： Bo-Geun Kim ,  Heung-Soo Lim ,  Jae-Woo Im

IPC: G11C11/34 ,  G11C16/06

CPC classification number: G11C16/12 ,  G11C16/3454

Abstract: A NOR flash memory device and related programming method are disclosed. The programming method includes programming data in a memory cell and, during a program verification operation, controlling the supply of current from a sense amplifier to the memory cell in relation to the value of the programmed data. Wherein a program verification operation is indicated, current is provided from the sense amplifier to the memory cell. Where a program verification operation is not indicated, current is cut off from the sense amplifier.

Abstract translation: 公开了一种NOR闪存器件及相关编程方法。 编程方法包括在存储器单元中编程数据，并且在程序验证操作期间，相对于编程数据的值控制从读出放大器到存储单元的电流供应。 其中指示程序验证操作，从读出放大器向存储单元提供电流。 在没有指示程序验证操作的情况下，从感测放大器切断电流。