公开(公告)号：US07495299B2

公开(公告)日：2009-02-24

申请号：US11544611

申请日：2006-10-10

申请人： Kazuhiko Aida ,  Junji Hirase ,  Hisashi Ogawa ,  Chiaki Kudo

发明人： Kazuhiko Aida ,  Junji Hirase ,  Hisashi Ogawa ,  Chiaki Kudo

IPC分类号： H01L29/78

CPC分类号： H01L21/82345 ,  H01L21/823437 ,  H01L21/823443 ,  H01L27/0207 ,  H01L29/665

摘要： The following steps are carried out: forming a gate electrode on a semiconductor substrate with a gate insulating film interposed therebetween, forming a dummy gate electrode on the semiconductor substrate with a dummy gate insulating film interposed therebetween and forming another dummy gate electrode on the semiconductor substrate with an insulating film for isolation interposed therebetween; forming a metal film on the semiconductor while exposing the gate electrode and covering the dummy gate electrodes; and subjecting the semiconductor substrate to heat treatment and thus siliciding at least an upper part of the gate electrode. Since the gate electrode is silicided and the dummy gate electrodes are non-silicided, this restrains a short circuit from being caused between the gate electrode and adjacent one of the dummy gate electrodes.

摘要翻译： 执行以下步骤：在半导体衬底上形成栅电极，其间插入栅极绝缘膜，在半导体衬底上形成具有虚拟栅绝缘膜的虚拟栅电极，并在半导体衬底上形成另一虚拟栅电极 其间插入有用于隔离的绝缘膜; 在半导体上形成金属膜，同时露出栅电极并覆盖伪栅电极; 对半导体基板进行热处理，至少使栅电极的上部被硅化。 由于栅电极是硅化的，并且虚拟栅电极是非硅化的，所以这抑制了在栅电极和相邻的一个虚拟栅电极之间的短路。

公开(公告)号：US20080067574A1

公开(公告)日：2008-03-20

申请号：US11819190

申请日：2007-06-26

申请人： Chiaki Kudo

发明人： Chiaki Kudo

IPC分类号： H01L29/788 ,  H01L21/44

CPC分类号： H01L21/823835 ,  H01L21/28097 ,  H01L21/823842 ,  H01L21/823871

摘要： A semiconductor device includes a first conductor and a second conductor electrically connected to each other to have the same potential. At least one of the first and second conductors has a fully silicided (FUSI) structure. A step having an overhang is formed at least at part of a boundary between the first and second conductors.

摘要翻译： 半导体器件包括彼此电连接以具有相同电位的第一导体和第二导体。 第一和第二导体中的至少一个具有完全硅化（FUSI）结构。 至少在第一和第二导体之间的边界的一部分处形成具有突出端的台阶。

公开(公告)号：US06982222B2

公开(公告)日：2006-01-03

申请号：US10923869

申请日：2004-08-24

申请人： Chiaki Kudo

发明人： Chiaki Kudo

IPC分类号： H01L21/4763

CPC分类号： G06F17/5077 ,  Y10S438/942

摘要： In an interconnection mask pattern generation, there are suppressed a decrease in reliability of an interconnection and a decrease in manufacture yield, which are resulted from use of an interconnection pattern generated with single minimum line width data for a semiconductor device or the like. When a layout interconnection pattern on a mask for an interconnection which connects functional elements to each other being arranged based on logical circuit data is generated, an interconnection pattern based on the minimum line width data is generated, an interconnection pattern based on the minimum line spacing data is also generated, and an interconnection pattern arranging a new interconnection boundary in the middle of both of them is then generated to be used as a final interconnection pattern, so that the interconnection pattern width becomes properly thick in width, thereby making it possible to improve reliability of the interconnection and suppress a decrease in manufacturing yield.

摘要翻译： 在互连掩模图案生成中，通过使用用于半导体器件等的单个最小线宽数据生成的互连图案，抑制了互连的可靠性的降低和制造成品率的降低。 当生成基于逻辑电路数据布置连接功能元件的互连的掩模上的布局布线图案时，基于最小线宽数据生成布线图形，基于最小线间距的互连图案 然后生成数据，并且生成在它们两者的中间布置新的互连边界的互连图案以用作最终互连图案，使得互连图案宽度变得适当地变宽，从而使得可以 提高互连的可靠性，抑制制造成品率的下降。

公开(公告)号：US06621123B1

公开(公告)日：2003-09-16

申请号：US09576436

申请日：2000-05-22

申请人： Takashi Nakabayashi ,  Chiaki Kudo

发明人： Takashi Nakabayashi ,  Chiaki Kudo

IPC分类号： H01L2701

CPC分类号： H01L29/0649 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78654 ,  H01L29/78696

摘要： On a semiconductor substrate of P-type silicon, an active area including a channel forming region with a smaller dimension along the gate width and a source region and a drain region extending along the gate length is formed so as to be surrounded with an isolation area of an insulating oxide film. On the isolation area on the semiconductor substrate and the channel forming region of the active area, a gate electrode is formed with a gate insulating oxide film sandwiched therebetween. A channel lower insulating layer is formed, out of the same insulating oxide film for the isolation area, merely in an area below the channel forming region below the gate electrode in the active area of the semiconductor substrate.

摘要翻译： 在P型硅的半导体基板上，沿着栅极宽度包括具有较小尺寸的沟道形成区域和沿着栅极长度延伸的源极区域和漏极区域的有源区域形成为被隔离区域包围 的绝缘氧化膜。 在半导体衬底上的隔离区域和有源区的沟道形成区域之间形成栅电极，栅极绝缘氧化膜夹在其间。 在半导体衬底的有源区域中，仅在与用于隔离区域的绝缘氧化物膜相同的绝缘氧化膜的沟道下绝缘层仅在栅电极下方的沟道形成区域之下的区域中形成。

公开(公告)号：US6093592A

公开(公告)日：2000-07-25

申请号：US872335

申请日：1997-06-10

申请人： Takashi Nakabayashi ,  Chiaki Kudo

发明人： Takashi Nakabayashi ,  Chiaki Kudo

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/01 ,  H01L29/06 ,  H01L29/76 ,  H01L29/786

CPC分类号： H01L29/0649 ,  H01L29/66772 ,  H01L29/78606 ,  H01L29/78654 ,  H01L29/78696

摘要： On a semiconductor substrate of P-type silicon, an active area including a channel forming region with a smaller dimension along the gate width and a source region and a drain region extending along the gate length is formed so as to be surrounded with an isolation area of an insulating oxide film. On the isolation area on the semiconductor substrate and the channel forming region of the active area, a gate electrode is formed with a gate insulating oxide film sandwiched therebetween. A channel lower insulating layer is formed, out of the same insulating oxide film for the isolation area, merely in an area below the channel forming region below the gate electrode in the active area of the semiconductor substrate.

摘要翻译： 在P型硅的半导体基板上，沿着栅极宽度包括具有较小尺寸的沟道形成区域和沿着栅极长度延伸的源极区域和漏极区域的有源区域形成为被隔离区域包围 的绝缘氧化膜。 在半导体衬底上的隔离区域和有源区的沟道形成区域之间形成栅电极，栅极绝缘氧化膜夹在其间。 在半导体衬底的有源区域中，仅在与用于隔离区域的绝缘氧化物膜相同的绝缘氧化膜的沟道下绝缘层仅在栅电极下方的沟道形成区域之下的区域中形成。

公开(公告)号：US20080067611A1

公开(公告)日：2008-03-20

申请号：US11896997

申请日：2007-09-07

申请人： Chiaki Kudo ,  Hisashi Ogawa

发明人： Chiaki Kudo ,  Hisashi Ogawa

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/42376 ,  H01L21/28123 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/0207 ,  H01L29/4238

摘要： A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region; and a first gate electrode formed on the isolation region and the active region and including a first region on the isolation region. The first region has a pattern width in a gate length direction larger than a pattern width of the first gate electrode on the active region. The first region includes a part having a film thickness different from a film thickness of the first gate electrode on the active region.

摘要翻译： 半导体器件包括：形成在半导体衬底中的隔离区; 由隔离区包围的有源区; 以及形成在所述隔离区域和所述有源区域上并且包括所述隔离区域上的第一区域的第一栅电极。 第一区域具有比有源区域上的第一栅电极的图案宽度大的栅极长度方向的图案宽度。 第一区域包括具有与活性区域上的第一栅电极的膜厚度不同的膜厚度的部分。

公开(公告)号：US20070131930A1

公开(公告)日：2007-06-14

申请号：US11544611

申请日：2006-10-10

申请人： Kazuhiko Aida ,  Junji Hirase ,  Hisashi Ogawa ,  Chiaki Kudo

发明人： Kazuhiko Aida ,  Junji Hirase ,  Hisashi Ogawa ,  Chiaki Kudo

IPC分类号： H01L23/58

CPC分类号： H01L21/82345 ,  H01L21/823437 ,  H01L21/823443 ,  H01L27/0207 ,  H01L29/665

摘要： The following steps are carried out: forming a gate electrode on a semiconductor substrate with a gate insulating film interposed therebetween, forming a dummy gate electrode on the semiconductor substrate with a dummy gate insulating film interposed therebeweeen and forming another dummy gate electrode on the semiconductor substrate with an insulating film for isolation interposed therebetween; forming a metal film on the semiconductor while exposing the gate electrode and covering the dummy gate electrodes; and subjecting the semiconductor substrate to heat treatment and thus siliciding at least an upper part of the gate electrode. Since the gate electrode is silicided and the dummy gate electrodes are non-silicided, this restrains a short circuit from being caused between the gate electrode and adjacent one of the dummy gate electrodes.

摘要翻译： 执行以下步骤：在半导体衬底上形成栅极电极，并在其间插入栅极绝缘膜，在半导体衬底上形成虚拟栅极电极，并在其上插入虚拟栅极绝缘膜，并在半导体衬底上形成另一个虚设栅电极 其间插入有用于隔离的绝缘膜; 在半导体上形成金属膜，同时露出栅电极并覆盖伪栅电极; 对半导体基板进行热处理，至少使栅电极的上部被硅化。 由于栅电极是硅化的，并且虚拟栅电极是非硅化的，所以这抑制了在栅电极和相邻的一个虚拟栅电极之间的短路。

公开(公告)号：US20070096183A1

公开(公告)日：2007-05-03

申请号：US11500940

申请日：2006-08-09

申请人： Hisashi Ogawa ,  Naoki Kotani ,  Susumu Akamatsu ,  Chiaki Kudo

发明人： Hisashi Ogawa ,  Naoki Kotani ,  Susumu Akamatsu ,  Chiaki Kudo

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L21/336 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/0629 ,  H01L27/0251 ,  H01L28/20

摘要： In a semiconductor device including a MIS transistor with a FUSI gate electrode and a polysilicon resistor, a portion of the polysilicon resistor provided in a contact formation region is silicided simultaneously with the gate electrode or an impurity diffusion region.

摘要翻译： 在包括具有FUSI栅电极的MIS晶体管和多晶硅电阻器的半导体器件中，设置在接触形成区域中的多晶硅电阻器的一部分与栅极电极或杂质扩散区域同时被硅化。

公开(公告)号：US20070093015A1

公开(公告)日：2007-04-26

申请号：US11488051

申请日：2006-07-18

申请人： Chiaki Kudo ,  Hisashi Ogawa

发明人： Chiaki Kudo ,  Hisashi Ogawa

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823835 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/0629 ,  H01L28/20

摘要： A semiconductor device includes a first field-effect transistor including a first gate electrode and a second field-effect transistor including a second gate electrode. The first gate electrode and the second gate electrode are integrated using a connecting portion and are fully silicided with a metal in such a manner that the fist and second gate electrodes have different metal contents. A diffusion preventing film for preventing the metal from diffusing between the first and second gate electrodes is formed in at least a portion of the connecting portion.

摘要翻译： 半导体器件包括第一场效应晶体管，其包括第一栅电极和包括第二栅极的第二场效应晶体管。 第一栅电极和第二栅电极使用连接部分集成，并且以金属完全硅化，使得第一和第二栅电极具有不同的金属含量。 在连接部分的至少一部分上形成用于防止金属在第一和第二栅电极之间扩散的扩散防止膜。

公开(公告)号：US20050129329A1

公开(公告)日：2005-06-16

申请号：US11003735

申请日：2004-12-06

申请人： Chiaki Kudo

发明人： Chiaki Kudo

IPC分类号： H01L27/148 ,  G06K9/40 ,  H04N5/335 ,  H04N5/367 ,  H04N5/369 ,  H04N5/372 ,  H04N5/378

CPC分类号： H04N5/372 ,  H04N5/3675 ,  H04N5/3728

摘要： When charges Q (x, y) transferred from an image inputting device 1 are to be converted into first signal intensities S′ (x, y) and signal processing is to be performed for the first signal intensity S′ (x, y) of a particular pixel, a maximum value Smax, a minimum value Smin and an average value Save are calculated from signal intensities S′ (x−1, y) and S′ (x+1, y) at adjacent pixels. When S′ (x, y)>Smax×A is satisfied, it is determined that the signal intensity S (x, y) at the particular pixel=Save×C (where A and C are coefficients), whereas when S′ (x, y)

摘要翻译： 当从图像输入装置1传送的电荷Q（x，y）被转换为第一信号强度S'（x，y）时，对第一信号强度S'（x，y）进行信号处理 根据相邻像素处的信号强度S'（x-1，y）和S'（x + 1，y）计算特定像素，最大值Smax，最小值Smin和平均值Save。 当满足S'（x，y）> SmaxxA时，确定特定像素处的信号强度S（x，y）= SavexC（其中A和C是系数），而当S'（x，y） 确定信号强度S（x，y）= SavexD（其中B和D是系数），并且执行处理以获得适当的强度S（x，y）