公开(公告)号：US20130099310A1

公开(公告)日：2013-04-25

申请号：US13710816

申请日：2012-12-11

Applicant: Chiao-Shun Chuang

Inventor： Chiao-Shun Chuang

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L27/0727 ,  H01L29/7806

Abstract: In one embodiment the present invention includes a semiconductor device. The semiconductor device comprises a first semiconductor region, a second semiconductor region and a trench region. The first semiconductor region is of a first conductivity type and a first conductivity concentration. The trench region includes a metal layer in contact with the first semiconductor region to form a metal-semiconductor junction. The second semiconductor region is adjacent to the first semiconductor region that has a second conductivity type and a second conductivity concentration. The second semiconductor region forms a PN junction with the first semiconductor region, and the trench region has a depth such that the metal-semiconductor junction is proximate to the PN junction.

Abstract translation: 在一个实施例中，本发明包括半导体器件。 半导体器件包括第一半导体区域，第二半导体区域和沟槽区域。 第一半导体区域是第一导电类型和第一电导率浓度。 沟槽区域包括与第一半导体区域接触以形成金属 - 半导体结的金属层。 第二半导体区域与具有第二导电类型和第二电导率浓度的第一半导体区域相邻。 第二半导体区域与第一半导体区域形成PN结，并且沟槽区域具有使得金属 - 半导体结接近PN结的深度。

公开(公告)号：US20090039448A1

公开(公告)日：2009-02-12

申请号：US11924615

申请日：2007-10-26

Applicant: Chiao-Shun Chuang ,  Fang-Chung Chen ,  Han-Ping David Shieh

Inventor： Chiao-Shun Chuang ,  Fang-Chung Chen ,  Han-Ping David Shieh

IPC: H01L31/02

CPC classification number: G02F1/133514 ,  G02F1/133345 ,  G02F1/133617 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2202/046 ,  G02F2202/36

Abstract: A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a semi-conductive layer, a gate insulator, a source and a drain. The gate insulator is located between the gate and the semi-conductive layer. A light shows a specific color after passing through the gate insulator. The source and the drain are disposed on the semi-conductive layer. A pixel structure and a liquid crystal display panel having the pixel structure are also provided. The liquid crystal display panel can display colorful images without disposing a color filter array additionally so that the manufacturing process of the liquid crystal panel is simple and the manufacturing cost of the liquid crystal panel is low.

Abstract translation: 设置在基板上的薄膜晶体管。 薄膜晶体管包括栅极，半导电层，栅极绝缘体，源极和漏极。 栅极绝缘体位于栅极和半导体层之间。 光通过栅极绝缘体后显示特定的颜色。 源极和漏极设置在半导体层上。 还提供了具有像素结构的像素结构和液晶显示面板。 液晶显示面板可以在不附加滤色器阵列的情况下显示彩色图像，使得液晶面板的制造过程简单，并且液晶面板的制造成本低。

公开(公告)号：US07265024B2

公开(公告)日：2007-09-04

申请号：US11329870

申请日：2006-01-10

Applicant: Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng

Inventor： Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng

IPC: H01L21/76 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/336 ,  H01L29/76

CPC classification number: H01L29/7811 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7813

Abstract: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.

Abstract translation: 引入了具有沟槽总线结构的DMOS器件。 沟槽总线结构包括形成在P基板上的场氧化物层和从场氧化物层的顶表面向下延伸到P衬底的下部的沟槽。 形成栅极氧化层和多晶硅母线，以填充沟槽作为总线结构的主要部分。 此外，在多晶硅总线和场氧化物层的顶部形成隔离层和金属线。 在隔离层中形成开口以形成多晶硅母线和金属线之间的连接。 在具体实施例中，同时形成DMOS器件的总线沟槽和栅极沟槽，同时形成多晶硅母线和栅电极。 因此，总线结构能够形成DMOS晶体管，而不需要用于定义多晶硅总线位置的任何光刻步骤。

公开(公告)号：US20070158647A1

公开(公告)日：2007-07-12

申请号：US11467165

申请日：2006-08-25

Applicant: Fang-Chung Chen ,  Chiao-Shun Chuang ,  Dong-Sian Chen ,  Li-Jen Kung ,  Yung-Sheng Lin ,  Chuan-Yi Wu

Inventor： Fang-Chung Chen ,  Chiao-Shun Chuang ,  Dong-Sian Chen ,  Li-Jen Kung ,  Yung-Sheng Lin ,  Chuan-Yi Wu

IPC: H01L29/08 ,  H01L35/24 ,  H01L51/00

CPC classification number: H01L51/105 ,  H01L51/057

Abstract: A junction structure of an organic semiconductor device including an organic semiconductor layer, a conductive layer and a modifying layer is provided. The modifying layer is formed between the organic semiconductor layer and the conductive layer, wherein the modifying layer includes an inorganic compound or an organic complex compound. An organic thin film transistor including a gate, a source/drain, a dielectric layer, an organic semiconductor layer and at least a modifying layer is also provided. The gate is electrically isolated from the source/drain. The dielectric layer is disposed between the gate and the source/drain. The organic semiconductor layer is disposed between the source and the drain. The modifying layer is disposed between the organic semiconductor layer and the source/drain, wherein the modifying layer includes an inorganic compound or an organic complex compound.

公开(公告)号：US06998315B2

公开(公告)日：2006-02-14

申请号：US11056450

申请日：2005-02-11

Applicant: Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

Inventor： Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/0661 ,  H01L29/41766 ,  H01L29/7802

Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench. A metal layer covers portions of the passivation layer on the side walls of the trench to expose a part of the passivation layer over the bottom surface of the trench.

Abstract translation: 本发明的实施例涉及一种为沟槽DMOS器件提供的终端结构，以减少由于在有源区域的边界处的电场拥挤而产生的电流泄漏及其制造方法。 在一个实施例中，沟槽DMOS器件的端接结构包括在衬底上的第一类型导电性衬底和第一类型导电性的外延层。 外延层具有比衬底更低的掺杂浓度。 在外延层内提供第二类导电体的主体区域。 沟槽延伸穿过衬底的有源区域和边缘之间的主体区域。 栅极氧化物层排列沟槽并且延伸到沟槽和有源区域之间的主体区域的上表面。 钝化层形成在栅极氧化层上，包括沟槽的侧壁和底表面。 金属层覆盖沟槽侧壁上的钝化层的部分，以使钝化层的一部分暴露在沟槽的底表面上。

公开(公告)号：US06855986B2

公开(公告)日：2005-02-15

申请号：US10652442

申请日：2003-08-28

Applicant: Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

Inventor： Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/772

CPC classification number: H01L29/7813 ,  H01L29/0661 ,  H01L29/41766 ,  H01L29/7802

Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench. A metal layer covers portions of the passivation layer on the side walls of the trench to expose a part of the passivation layer over the bottom surface of the trench.

Abstract translation: 本发明的实施例涉及一种为沟槽DMOS器件提供的终端结构，以减少由于在有源区域的边界处的电场拥挤而产生的电流泄漏及其制造方法。 在一个实施例中，沟槽DMOS器件的端接结构包括在衬底上的第一类型导电性衬底和第一类型导电性的外延层。 外延层具有比衬底更低的掺杂浓度。 在外延层内提供第二类导电体的主体区域。 沟槽延伸穿过衬底的有源区域和边缘之间的主体区域。 栅极氧化物层排列沟槽并且延伸到沟槽和有源区域之间的主体区域的上表面。 钝化层形成在栅极氧化层上，包括沟槽的侧壁和底表面。 金属层覆盖沟槽侧壁上的钝化层的部分，以使钝化层的一部分暴露在沟槽的底表面上。

公开(公告)号：US08907325B2

公开(公告)日：2014-12-09

申请号：US11924615

申请日：2007-10-26

Applicant: Chiao-Shun Chuang ,  Fang-Chung Chen ,  Han-Ping David Shieh

Inventor： Chiao-Shun Chuang ,  Fang-Chung Chen ,  Han-Ping David Shieh

IPC: H01L29/08 ,  H01L35/24 ,  H01L29/10 ,  G02F1/1335 ,  G02F1/1333 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: G02F1/133514 ,  G02F1/133345 ,  G02F1/133617 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2202/046 ,  G02F2202/36

Abstract: A thin film transistor disposed on a substrate is provided. The thin film transistor includes a gate, a semi-conductive layer, a gate insulator, a source and a drain. The gate insulator is located between the gate and the semi-conductive layer. A light shows a specific color after passing through the gate insulator. The source and the drain are disposed on the semi-conductive layer. A pixel structure and a liquid crystal display panel having the pixel structure are also provided. The liquid crystal display panel can display colorful images without disposing a color filter array additionally so that the manufacturing process of the liquid crystal panel is simple and the manufacturing cost of the liquid crystal panel is low.

Abstract translation: 设置在基板上的薄膜晶体管。 薄膜晶体管包括栅极，半导电层，栅极绝缘体，源极和漏极。 栅极绝缘体位于栅极和半导体层之间。 光通过栅极绝缘体后显示特定的颜色。 源极和漏极设置在半导体层上。 还提供了具有像素结构的像素结构和液晶显示面板。 液晶显示面板可以在不附加滤色器阵列的情况下显示彩色图像，使得液晶面板的制造过程简单，并且液晶面板的制造成本低。

公开(公告)号：US20140054683A1

公开(公告)日：2014-02-27

申请号：US13646906

申请日：2012-10-08

Applicant: Chiao-Shun Chuang ,  Tony Huang

Inventor： Chiao-Shun Chuang ,  Tony Huang

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, the present invention includes a semiconductor power device. The semiconductor power device comprises a trenched gate and a trenched field region. The trenched gate is disposed vertically within a trench in a semiconductor substrate. The trenched field, region is disposed vertically within the trench and below the trenched gate. A lower portion of the trenched field region tapers to dispose an electric field.

Abstract translation: 在一个实施例中，本发明包括半导体功率器件。 半导体功率器件包括沟槽栅极和沟槽场区域。 沟槽栅极垂直设置在半导体衬底的沟槽内。 沟槽场区域垂直设置在沟槽内并在沟槽栅极下方。 沟槽场区域的下部逐渐变细以设置电场。

公开(公告)号：US20110133271A1

公开(公告)日：2011-06-09

申请号：US12630088

申请日：2009-12-03

Applicant: Chiao-Shun Chuang

Inventor： Chiao-Shun Chuang

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L29/7827 ,  H01L27/0727

Abstract: In one embodiment the present invention includes a semiconductor device. The semiconductor device comprises a first semiconductor region, a second semiconductor region and a trench region. The first semiconductor region is of a first conductivity type and a first conductivity concentration. The trench region includes a metal layer in contact with the first semiconductor region to form a metal-semiconductor junction. The second semiconductor region is adjacent to the first semiconductor region that has a second conductivity type and a second conductivity concentration. The second semiconductor region forms a PN junction with the first semiconductor region, and the trench region has a depth such that the metal-semiconductor junction is proximate to the PN junction.

Abstract translation: 在一个实施例中，本发明包括半导体器件。 半导体器件包括第一半导体区域，第二半导体区域和沟槽区域。 第一半导体区域是第一导电类型和第一电导率浓度。 沟槽区域包括与第一半导体区域接触以形成金属 - 半导体结的金属层。 第二半导体区域与具有第二导电类型和第二电导率浓度的第一半导体区域相邻。 第二半导体区域与第一半导体区域形成PN结，并且沟槽区域具有使得金属 - 半导体结接近PN结的深度。

公开(公告)号：US20080206944A1

公开(公告)日：2008-08-28

申请号：US11709715

申请日：2007-02-23

Applicant: Chiao-Shun Chuang ,  Hung-Ta Weng

Inventor： Chiao-Shun Chuang ,  Hung-Ta Weng

IPC: H01L21/8234

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/66719 ,  H01L29/66734 ,  H01L29/7806

Abstract: A method uses simplified processes to complete the forming of the trench DMOS transistors and Schottky contacts. In the processes, only four masks, i.e. a trench pattern mask, a contact-hole pattern mask, a P+ contact pattern mask and a conductive-wire pattern mask, are applied to create desired trench DMOS transistors. In addition to the trench DMOS transistors, a Schottky contact is simultaneously formed at a junction between a conductive layer and a doped body region in the trench DMOS transistors without additional photolithography process.

Abstract translation: 一种方法使用简化的过程来完成沟槽DMOS晶体管和肖特基触点的形成。 在该过程中，仅施加四个掩模，即沟槽图案掩模，接触孔图案掩模，P +接触图案掩模和导线图案掩模，以产生所需的沟槽DMOS晶体管。 除了沟槽DMOS晶体管之外，肖特基接触同时形成在沟道DMOS晶体管中的导电层和掺杂体区之间的结处，而不需要额外的光刻工艺。