公开(公告)号：US20060091490A1

公开(公告)日：2006-05-04

申请号：US11077478

申请日：2005-03-10

申请人： Hung-Wei Chen ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Min-Hwa Chi ,  Chung-Hu Ke

发明人： Hung-Wei Chen ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Min-Hwa Chi ,  Chung-Hu Ke

IPC分类号： H01L31/105

CPC分类号： H01L29/7391 ,  H01L29/868

摘要： A gated p-i-n diode and a method for forming the same. The gated p-i-n diode comprises: a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode on the gate dielectric; a source gate spacer and a drain gate spacer along respective edges of the gate dielectric and the gate electrode; a source doped with a first type of dopant substantially under the source gate spacer wherein the source has a horizontal distance from a first edge of the gate electrode; a drain doped with the opposite type of the source substantially under the drain spacer and substantially aligned horizontally with a second edge of the gate electrode; a source silicide adjacent the source; and a drain silicide adjacent the drain.

摘要翻译： 门式p-i-n二极管及其形成方法。 门控p-i-n二极管包括：半导体衬底; 半导体衬底上的栅极电介质; 栅电极上的栅电极; 源栅极间隔物和漏极栅极间隔物，沿着栅极电介质和栅电极的相应边缘; 源极掺杂有基本上在源栅极间隔物下方的第一类型掺杂剂的源，其中源极与栅电极的第一边缘具有水平距离; 基本上在所述漏极间隔物的下方掺杂有相反类型的源极的漏极，并且与所述栅极电极的第二边缘基本对准; 邻近源极的源硅化物; 和漏极附近的漏极硅化物。

公开(公告)号：US20110223727A1

公开(公告)日：2011-09-15

申请号：US13113530

申请日：2011-05-23

申请人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

发明人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/47 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7843

摘要： A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.

摘要翻译： 半导体结构包括半导体衬底和在半导体衬底的表面处的NMOS器件，其中NMOS器件包括肖特基源极/漏极延伸区域。 半导体结构还包括在半导体衬底的表面处的PMOS器件，其中PMOS器件包括仅包含非金属材料的源极/漏极延伸区域。 可以为PMOS器件和NMOS器件形成肖特基源极/漏极延伸区域，其中通过在具有低价带的半导体层上形成PMOS器件来减小PMOS器件的肖特基势垒高度。

公开(公告)号：US07803718B2

公开(公告)日：2010-09-28

申请号：US12260674

申请日：2008-10-29

申请人： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

发明人： Chih-Hsin Ko ,  Tzu-Juei Wang ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC分类号： H01L23/31

CPC分类号： H01L21/8249 ,  H01L21/823807 ,  H01L27/0623 ,  H01L29/7843

摘要： A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT.

摘要翻译： 提供了通过机械单轴应变增强性能的BiCMOS器件。 本发明的第一实施例包括形成在衬底的不同区域上的NMOS晶体管，PMOS晶体管和双极晶体管。 具有拉伸应力的第一接触蚀刻停止层形成在NMOS晶体管上，并且在PMOS晶体管和双极晶体管上形成具有压应力的第二接触蚀刻停止层，从而允许每个器件的增强。 除了应力接触蚀刻停止层之外，另一实施例还包括PMOS晶体管和NMOS晶体管中的应变通道区域以及BJT中的应变基极。

公开(公告)号：US20070052027A1

公开(公告)日：2007-03-08

申请号：US11220176

申请日：2005-09-06

申请人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

发明人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee ,  Min-Hwa Chi

IPC分类号： H01L27/01

CPC分类号： H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0922 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/785

摘要： A CMOS device is provided. A semiconductor device comprises a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation represented by a family of Miller indices comprising {i,j,k}, the second region having a second crystal orientation represented a family of Miller indices comprising {l,m,n}, wherein l2+m2+n2>i2+j2+k2. Alternative embodiments further comprise an NMOSFET formed on the first region, and a PMOSFET formed on the second region. Embodiments further comprise a Schottky contact formed with at least one of a the NMOSFET or PMOSFET.

摘要翻译： 提供CMOS器件。 半导体器件包括衬底，衬底具有第一区域和第二区域，第一区域具有由包括{i，j，k}的米勒指数族代表的第一晶体取向，第二区域具有第二晶体取向 代表了包含{l，m，n}的米勒指数族，其中l 2+ + m 2 + 2 + 2 2 / 2 + 2＆lt; 2＆gt; 2＆gt; 2＆lt; 2＆gt; 替代实施例还包括形成在第一区域上的NMOSFET和形成在第二区域上的PMOSFET。 实施例还包括由NMOSFET或PMOSFET中的至少一个形成的肖特基接触。

公开(公告)号：US08426298B2

公开(公告)日：2013-04-23

申请号：US13113530

申请日：2011-05-23

申请人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

发明人： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC分类号： H01L21/28 ,  H01L21/44

CPC分类号： H01L21/823814 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/47 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/66643 ,  H01L29/7843

摘要： A semiconductor structure includes a semiconductor substrate, and an NMOS device at a surface of the semiconductor substrate, wherein the NMOS device comprises a Schottky source/drain extension region. The semiconductor structure further includes a PMOS device at the surface of the semiconductor substrate, wherein the PMOS device comprises a source/drain extension region comprising only non-metal materials. Schottky source/drain extension regions may be formed for both PMOS and NMOS devices, wherein the Schottky barrier height of the PMOS device is reduced by forming the PMOS device over a semiconductor layer having a low valence band.

摘要翻译： 半导体结构包括半导体衬底和在半导体衬底的表面处的NMOS器件，其中NMOS器件包括肖特基源/漏延伸区域。 半导体结构还包括在半导体衬底的表面处的PMOS器件，其中PMOS器件包括仅包含非金属材料的源极/漏极延伸区域。 可以为PMOS器件和NMOS器件形成肖特基源极/漏极延伸区域，其中通过在具有低价带的半导体层上形成PMOS器件来减小PMOS器件的肖特基势垒高度。

公开(公告)号：US08039284B2

公开(公告)日：2011-10-18

申请号：US11640713

申请日：2006-12-18

申请人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

发明人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC分类号： H01L21/00 ,  H01L29/84

CPC分类号： H01L21/823807 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7843

摘要： A method for forming a semiconductor structure includes: providing a semiconductor substrate; forming an NMOS device at a surface of the semiconductor substrate, which comprises forming a first source/drain electrode on a first source/drain region of the NMOS device, wherein the first source/drain electrode has a first barrier height; forming a PMOS device at the surface of the semiconductor substrate comprising forming a second source/drain electrode on a second source/drain region of the PMOS device, wherein the second source/drain electrode has a second barrier height, and wherein the first barrier height is different from the second barrier height; forming a first stressed film having a first intrinsic stress over the NMOS device; and forming a second stressed film having a second intrinsic stress over the PMOS device, wherein the first intrinsic stress is more tensile than the second intrinsic stress.

摘要翻译： 一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底的表面上形成NMOS器件，其包括在所述NMOS器件的第一源极/漏极区域上形成第一源极/漏极，其中所述第一源极/漏极具有第一势垒高度; 在所述半导体衬底的表面上形成PMOS器件，包括在所述PMOS器件的第二源极/漏极区域上形成第二源极/漏极，其中所述第二源极/漏极具有第二势垒高度，并且其中所述第一势垒高度 与第二屏障高度不同; 在NMOS器件上形成具有第一固有应力的第一应力膜; 以及在所述PMOS器件上形成具有第二固有应力的第二应力膜，其中所述第一本征应力比所述第二固有应力更具拉伸力。

公开(公告)号：US07569896B2

公开(公告)日：2009-08-04

申请号：US11438711

申请日：2006-05-22

申请人： Chih-Hsin Ko ,  Chung-Hu Ke ,  Hung-Wei Chen ,  Wen-Chin Lee

发明人： Chih-Hsin Ko ,  Chung-Hu Ke ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC分类号： H01L29/78

CPC分类号： H01L29/6656 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843

摘要： A MOS device having optimized stress in the channel region and a method for forming the same are provided. The MOS device includes a gate over a substrate, a gate spacer on a sidewall of the gate wherein a non-silicide region exists under the gate spacer, a source/drain region comprising a recess in the substrate, and a silicide region on the source/drain region. A step height is formed between a higher portion of the silicide region and a lower portion of the silicide region. The recess is spaced apart from a respective edge of a non-silicide region by a spacing. The step height and the spacing preferably have a ratio of less than or equal to about 3. The width of the non-silicide region and the step height preferably have a ratio of less than or equal to about 3. The MOS device is preferably an NMOS device.

摘要翻译： 提供了在通道区​​域中具有优化的应力的MOS器件及其形成方法。 MOS器件包括在衬底上的栅极，栅极侧壁上的栅极间隔物，其中在栅极间隔物下方存在非硅化物区域，在衬底中包含凹陷的源极/漏极区域和源极上的硅化物区域 /漏区。 在硅化物区域的较高部分和硅化物区域的下部之间形成台阶高度。 凹槽与非硅化物区域的相应边缘间隔一定距离。 台阶高度和间距优选具有小于或等于约3的比率。非硅化物区域的宽度和台阶高度优选具有小于或等于约3的比率。MOS器件优选为 NMOS器件。

公开(公告)号：US20080145984A1

公开(公告)日：2008-06-19

申请号：US11640713

申请日：2006-12-18

申请人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

发明人： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7843

摘要： A method for forming a semiconductor structure includes: providing a semiconductor substrate; forming an NMOS device at a surface of the semiconductor substrate, which comprises forming a first source/drain electrode on a first source/drain region of the NMOS device, wherein the first source/drain electrode has a first barrier height; forming a PMOS device at the surface of the semiconductor substrate comprising forming a second source/drain electrode on a second source/drain region of the PMOS device, wherein the second source/drain electrode has a second barrier height, and wherein the first barrier height is different from the second barrier height; forming a first stressed film having a first intrinsic stress over the NMOS device; and forming a second stressed film having a second intrinsic stress over the PMOS device, wherein the first intrinsic stress is more tensile than the second intrinsic stress.

摘要翻译： 一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底的表面上形成NMOS器件，其包括在所述NMOS器件的第一源极/漏极区域上形成第一源极/漏极，其中所述第一源极/漏极具有第一势垒高度; 在所述半导体衬底的表面上形成PMOS器件，包括在所述PMOS器件的第二源极/漏极区域上形成第二源极/漏极电极，其中所述第二源极/漏极具有第二势垒高度，并且其中所述第一势垒高度 与第二屏障高度不同; 在NMOS器件上形成具有第一固有应力的第一应力膜; 以及在所述PMOS器件上形成具有第二固有应力的第二应力膜，其中所述第一本征应力比所述第二固有应力更具拉伸力。

公开(公告)号：US07355262B2

公开(公告)日：2008-04-08

申请号：US11378907

申请日：2006-03-17

申请人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

发明人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

IPC分类号： H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L21/76224 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1037 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on the semiconductor substrate, and forming a MOS device in the diffusion region. The DTE causes silicon migration, forming a rounded or a T-shaped surface of the diffusion regions. The method may further include recessing a portion of the diffusion region before performing the DTE. The diffusion region has a slanted surface after performing the DTE.

摘要翻译： 半导体结构使用扩散地形工程（DTE）形成。 优选的方法包括提供半导体衬底，形成限定扩散区域的沟槽隔离区域，在半导体衬底上的含氢环境中进行DTE，以及在扩散区域中形成MOS器件。 DTE导致硅迁移，形成扩散区域的圆形或T形表面。 该方法还可以包括在执行DTE之前使扩散区的一部分凹陷。 在执行DTE之后，扩散区域具有倾斜表面。

公开(公告)号：US20070215936A1

公开(公告)日：2007-09-20

申请号：US11378907

申请日：2006-03-17

申请人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

发明人： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L21/76224 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1037 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on the semiconductor substrate, and forming a MOS device in the diffusion region. The DTE causes silicon migration, forming a rounded or a T-shaped surface of the diffusion regions. The method may further include recessing a portion of the diffusion region before performing the DTE. The diffusion region has a slanted surface after performing the DTE.

摘要翻译： 半导体结构使用扩散地形工程（DTE）形成。 优选的方法包括提供半导体衬底，形成限定扩散区域的沟槽隔离区域，在半导体衬底上的含氢环境中进行DTE，以及在扩散区域中形成MOS器件。 DTE导致硅迁移，形成扩散区域的圆形或T形表面。 该方法还可以包括在执行DTE之前使扩散区的一部分凹陷。 在执行DTE之后，扩散区域具有倾斜表面。