公开(公告)号：US20090077529A1

公开(公告)日：2009-03-19

申请号：US12269687

申请日：2008-11-12

申请人： TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

发明人： TOSHIYA KOTANI ,  Shigeki Nojima ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

摘要翻译： 公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法，其包括提取从设计图案的顶点延伸的两个边缘中的至少一个，测量提取的边缘的长度， 确定测量的边缘的长度是否短于预定值，如果确定提取的边缘的长度短于预定值，则提取连接到所提取的边缘的两个顶点，并且重新设计匹配的设计模式 两个提取的顶点的位置彼此相对。

公开(公告)号：US07213226B2

公开(公告)日：2007-05-01

申请号：US10920397

申请日：2004-08-18

申请人： Toshiya Kotani ,  Shigeki Nojima

发明人： Toshiya Kotani ,  Shigeki Nojima

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A method of correcting a finish pattern dimension by using OPC when a design pattern is formed on a wafer, including selecting and determining a first design pattern included in the design pattern; acquiring a measurement value of a first finish pattern dimension when the first design pattern is formed on a wafer; determining a first calculation model by using the first finish pattern dimension; selecting and determining a second design pattern from the design pattern except for the first design pattern; performing first simulation by using the first calculation model, and calculating a second finish pattern dimension when the second design pattern is formed on a wafer; determining a second calculation model for performing second simulation which is faster than the first simulation, by using the first and second finish pattern dimensions; and performing the second simulation by using the second calculation model, and calculating a third finish pattern dimension of a third design pattern of the design pattern except for the first and second design patterns.

摘要翻译： 一种当在晶片上形成设计图案时通过使用OPC来校正精加工图案尺寸的方法，包括选择和确定包括在设计图案中的第一设计图案; 当在晶片上形成第一设计图案时，获取第一精加工图案尺寸的测量值; 通过使用所述第一完成图案维度来确定第一计算模型; 从除了第一设计图案之外的设计图案中选择和确定第二设计图案; 通过使用第一计算模型执行第一模拟，以及当在晶片上形成第二设计图案时计算第二精加工图案尺寸; 通过使用第一和第二完成图案尺寸，确定用于执行比第一模拟更快的第二模拟的第二计算模型; 以及通过使用所述第二计算模型执行所述第二模拟，以及计算除了所述第一和第二设计图案之外的所述设计图案的第三设计图案的第三精加工图案尺寸。

公开(公告)号：US20070019058A1

公开(公告)日：2007-01-25

申请号：US11485554

申请日：2006-07-13

申请人： Toshiya Kotani ,  Shigeki Nojima ,  Shoji Mimotogi

发明人： Toshiya Kotani ,  Shigeki Nojima ,  Shoji Mimotogi

IPC分类号： B41J2/385

CPC分类号： G03F7/70433 ,  G03F7/705

摘要： A lithography simulation method includes: taking in design data of a pattern to be formed on a substrate and mask data to prepare a mask pattern used in forming a latent image of the pattern on the substrate by transmission of an energy ray; obtaining the latent image of the pattern by calculation of an intensity of the energy ray; locally changing, at least in a portion corresponding to a pattern to be interested, a relative position in a direction of the intensity of the energy ray between a latent image curve and a reference intensity line in accordance with a distance between the pattern to be interested and a pattern of a neighboring region, the latent image curve being an intensity distribution curve of the energy ray constituting the latent image, the reference intensity line being defined to specify a position of an edge of the pattern to be interested; and calculating a distance between intersections of a portion of the latent image curve corresponding to the pattern to be interested and the reference intensity line in the changed relative position to define an interested line width of the pattern to be interested.

摘要翻译： 光刻模拟方法包括：获取要在基板上形成的图案的设计数据，并且掩模数据，以通过透射能量线来制备用于在基板上形成图案的潜像所使用的掩模图案; 通过计算能量射线的强度来获得图案的潜像; 至少在与感兴趣的图案对应的部分中，根据感兴趣的图案之间的距离，在潜像图像曲线和参考强度线之间的能量射线的强度的方向上的相对位置 以及相邻区域的图案，所述潜像曲线是构成所述潜像的能量射线的强度分布曲线，所述基准强度线被定义为指定所述图案的边缘的位置; 以及计算与感兴趣的图案对应的潜在图像曲线的一部分的交点与变化的相对位置中的基准强度线之间的距离，以定义感兴趣的图案的感兴趣的线宽。

公开(公告)号：US20060033049A1

公开(公告)日：2006-02-16

申请号：US11200176

申请日：2005-08-10

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Soichi Inoue

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Soichi Inoue

IPC分类号： G21K5/10

CPC分类号： H01J37/3026 ,  G03F1/36 ,  G03F1/68

摘要： A design pattern data preparing method including preparing first mask pattern data based on first design pattern data, predicting a wafer pattern to be formed on a wafer corresponding to the first mask pattern based on the first mask pattern data, judging whether or not a finite difference between the predicted wafer pattern and the pattern to be formed on the wafer is within a predetermined allowable variation amount, correcting a portion of the first design pattern data selectively, the portion including a part corresponding to the finite difference when the finite difference is not within the allowable variation amount, and preparing second design pattern data by synthesizing the first mask pattern data corresponding to the portion including the part selectively corrected and data obtained by eliminating the first mask pattern data corresponding to the portion including the part selectively corrected from the first mask pattern data.

公开(公告)号：US20120198396A1

公开(公告)日：2012-08-02

申请号：US13237854

申请日：2011-09-20

申请人： Masanari KAJIWARA ,  Sachiko Kobayashi ,  Satoshi Tanaka ,  Kazuhiro Takahata ,  Shigeki Nojima ,  Toshiya Kotani ,  Shimon Maeda

发明人： Masanari KAJIWARA ,  Sachiko Kobayashi ,  Satoshi Tanaka ,  Kazuhiro Takahata ,  Shigeki Nojima ,  Toshiya Kotani ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： H01L22/20 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of optimizing a semiconductor device manufacturing process according to an embodiment is a method of optimizing a semiconductor device manufacturing process in which a pattern based on circuit design is formed. The method of optimizing a semiconductor device manufacturing process according to the embodiment includes: at the time of calculation of a statistic amount based on a distribution of differences at a plurality of sites between a pattern formed by a first exposing apparatus in a first condition and a pattern formed by a second exposing apparatus in a second condition, calculating the statistic amount after applying weighting to the differences based on information on an electrical characteristic; and repeating the calculating with the second condition being changed, and selecting an condition in which the total sum becomes a minimum or equal to or less than a standard value as an optimized condition of the second exposing apparatus.

摘要翻译： 根据实施例的优化半导体器件制造工艺的方法是优化其中形成基于电路设计的图案的半导体器件制造工艺的方法。 根据实施例的半导体器件制造方法的优化方法包括：在基于在第一状态下由第一曝光装置形成的图案与第一状态之间的多个位置处的差异的分布的统计量的计算时， 在第二状态下由第二曝光装置形成的图案，基于关于电特性的信息对所述差进行加权计算后的统计量; 并重复进行第二条件的计算，并且选择总和变为最小或等于或小于标准值的条件作为第二曝光装置的优化条件。

公开(公告)号：US08078996B2

公开(公告)日：2011-12-13

申请号：US12457751

申请日：2009-06-19

申请人： Kyoko Izuha ,  Shigeki Nojima ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Kyoko Izuha ,  Shigeki Nojima ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F17/50

CPC分类号： G03F7/70441 ,  G03F1/36

摘要： A pattern verification method includes preparing a desired pattern and a mask pattern forming the desired pattern on a substrate, defining at least one evaluation point on an edge of the desired pattern, defining at least one process parameter to compute the transferred/formed pattern, defining a reference value and a variable range for each of the process parameters, and computing a positional displacement for each first points corresponding to the evaluation point, first points computed using correction mask pattern and a plurality of combinations of parameter values obtained by varying the process parameters within the variable range or within the respective variable ranges. The positional displacement is a displacement between first point and the evaluation point. The method further includes computing a statistics of the positional displacements for each of the evaluation points, and outputting information modifying the mask pattern according to the statistics.

摘要翻译： 模式验证方法包括在衬底上制备期望图案和形成期望图案的掩模图案，在期望图案的边缘上限定至少一个评估点，限定至少一个过程参数以计算所转移/形成的图案，定义 针对每个处理参数的参考值和可变范围，并且计算与评估点相对应的每个第一点的位置偏移，使用校正掩模图案计算的第一点和通过改变处理参数获得的参数值的多个组合 在可变范围内或在相应的可变范围内。 位置偏移是第一点与评价点之间的位移。 该方法还包括计算每个评估点的位置偏移的统计量，并根据统计信息输出修改掩模图案的信息。

公开(公告)号：US07949967B2

公开(公告)日：2011-05-24

申请号：US12269705

申请日：2008-11-12

申请人： Toshiya Kotani ,  Shigeki Nojima ,  Shimon Maeda

发明人： Toshiya Kotani ,  Shigeki Nojima ,  Shimon Maeda

IPC分类号： G06F17/50

CPC分类号： G03F1/36

摘要： A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.

摘要翻译： 公开了一种相对于设计图案的微小步骤校正设计图案的设计图案校正方法，其包括提取从设计图案的顶点延伸的两个边缘中的至少一个，测量提取的边缘的长度， 确定测量的边缘的长度是否短于预定值，如果确定提取的边缘的长度短于预定值，则提取连接到所提取的边缘的两个顶点，并且重新设计匹配的设计模式 两个提取的顶点的位置彼此。

公开(公告)号：US20090019418A1

公开(公告)日：2009-01-15

申请号：US12222479

申请日：2008-08-11

申请人： Toshiya Kotani ,  Shigeki Nojima ,  Shoji Mimotogi

发明人： Toshiya Kotani ,  Shigeki Nojima ,  Shoji Mimotogi

IPC分类号： G06F17/50 ,  G06K9/00

CPC分类号： G03F7/70433 ,  G03F7/705

摘要： A lithography simulation method includes: taking in design data of a pattern to be formed on a substrate and mask data to prepare a mask pattern used in forming a latent image of the pattern on the substrate by transmission of an energy ray; obtaining the latent image of the pattern by calculation of an intensity of the energy ray; locally changing, at least in a portion corresponding to a pattern to be interested, a relative position in a direction of the intensity of the energy ray between a latent image curve and a reference intensity line in accordance with a distance between the pattern to be interested and a pattern of a neighboring region, the latent image curve being an intensity distribution curve of the energy ray constituting the latent image, the reference intensity line being defined to specify a position of an edge of the pattern to be interested; and calculating a distance between intersections of a portion of the latent image curve corresponding to the pattern to be interested and the reference intensity line in the changed relative position to define an interested line width of the pattern to be interested.

摘要翻译： 光刻模拟方法包括：获取要在基板上形成的图案的设计数据，并且掩模数据，以通过透射能量线来制备用于在基板上形成图案的潜像所使用的掩模图案; 通过计算能量射线的强度来获得图案的潜像; 至少在与感兴趣的图案对应的部分中，根据感兴趣的图案之间的距离，在潜像图像曲线和参考强度线之间的能量射线的强度的方向上的相对位置 以及相邻区域的图案，所述潜像曲线是构成所述潜像的能量射线的强度分布曲线，所述基准强度线被定义为指定所述图案的边缘的位置; 以及计算与感兴趣的图案对应的潜在图像曲线的一部分的交点与变化的相对位置中的基准强度线之间的距离，以定义感兴趣的图案的感兴趣的线宽。

公开(公告)号：US20050257188A1

公开(公告)日：2005-11-17

申请号：US11115187

申请日：2005-04-27

申请人： Toshiya Kotani ,  Shigeki Nojima ,  Kazuhito Kobayashi

发明人： Toshiya Kotani ,  Shigeki Nojima ,  Kazuhito Kobayashi

IPC分类号： G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F7/20 ,  G06F17/50 ,  G11B5/60 ,  H01L21/027

CPC分类号： G03F1/36

摘要： There is disclosed a pattern correcting method comprising extracting a correction pattern, at least the one or more correction patterns being included in a first design pattern formed on a substrate, acquiring layout information from the first design pattern, the layout information affecting a finished plane shape of the correction pattern on the substrate, determining contents of correction onto the correction pattern on the basis of the layout information, generating a design pattern-2 corresponding to the layout information so as to be associated with the correction pattern, and correcting the correction pattern in accordance with the contents of correction corresponding to the design pattern-2.

摘要翻译： 公开了一种图案校正方法，包括提取校正图案，至少一个或多个校正图案包括在形成在基板上的第一设计图案中，从第一设计图案获取布局信息，影响成品平面形状的布局信息 基于所述布局信息确定校正图案的校正内容，生成与所述布局信息对应的设计图案-2以与所述校正图案相关联，以及校正所述校正图案 按照与设计模式相对应的修正内容2。

公开(公告)号：US20050250022A1

公开(公告)日：2005-11-10

申请号：US11068896

申请日：2005-03-02

申请人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Koji Hashimoto ,  Soichi Inoue

发明人： Toshiya Kotani ,  Satoshi Tanaka ,  Shigeki Nojima ,  Koji Hashimoto ,  Soichi Inoue

IPC分类号： G03C5/00 ,  G03F1/14 ,  G03F9/00 ,  G06F17/50 ,  G06K9/00

CPC分类号： G06F17/5068 ,  G03F1/36

摘要： A pattern correcting method for correcting a design pattern to form a desired pattern on a wafer is disclosed, which comprises defining an allowable dimensional change quantity of each of design patterns, defining a pattern correction condition for the each design pattern based on the allowable dimensional change quantity defined for the each design pattern, and correcting the each design pattern based on the pattern correction condition defined for the each design pattern.

摘要翻译： 公开了一种用于校正在晶片上形成期望图案的设计图案的图案校正方法，其包括限定每个设计图案的允许尺寸变化量，基于允许的尺寸变化来定义每个设计图案的图案校正条件 并且基于为每个设计图案定义的图案校正条件来校正每个设计图案。