公开(公告)号：US06617189B1

公开(公告)日：2003-09-09

申请号：US10063949

申请日：2002-05-28

Applicant: Tze-Jing Chen ,  Ching-Chung Chen ,  Tung-Hu Lin ,  Chen-Bin Lin ,  Chi-Rong Lin

Inventor： Tze-Jing Chen ,  Ching-Chung Chen ,  Tung-Hu Lin ,  Chen-Bin Lin ,  Chi-Rong Lin

IPC: H01L2100

CPC classification number: H01L27/14685 ,  H01L27/14621 ,  H01L27/14627

Abstract: A method of fabricating an image sensor on a semiconductor substrate including a sensor array region is introduced. First, an R/G/B color filter array (CFA) is formed on portions of the semiconductor substrate corresponding to the sensor array region. Then, a spacer layer is formed on the R/G/B CFA, and a plurality of U-lens is formed on the spacer layer corresponding to the R/G/B CFA. Afterwards, a buffer layer is coated to fill a space between the U-lens, and a low-temperature passivation layer is deposited on the buffer layer and the U-lens at a temperature of about 300° C. or less to prevent the R/G/B CFA from damage.

Abstract translation: 引入了在包括传感器阵列区域的半导体衬底上制造图像传感器的方法。 首先，在对应于传感器阵列区域的半导体衬底的部分上形成R / G / B滤色器阵列（CFA）。 然后，在R / G / B CFA上形成间隔层，在对应于R / G / B CFA的间隔层上形成多个U型透镜。 然后，涂覆缓冲层以填充U型透镜之间的空间，并且在约300℃或更低的温度下在缓冲层和U型透镜上沉积低温钝化层以防止R / G / B CFA从损坏。

公开(公告)号：US06376359B1

公开(公告)日：2002-04-23

申请号：US09080082

申请日：1998-05-15

Applicant: Yei-Hsiung Lin ,  Chen-Bin Lin ,  Chin-Chun Huang

Inventor： Yei-Hsiung Lin ,  Chen-Bin Lin ,  Chin-Chun Huang

IPC: H01L214763

CPC classification number: H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing metallic interconnects capable of reducing internal stress inside the metallic layer. The method comprises the steps of forming a silicon-rich oxide layer both before and after the formation of a metallic layer. Therefore, the metallic layer is fully enclosed by silicon-rich oxide layers and any direct contact between the metallic layer and any silicon dioxide layer is avoided. Since the quantity of silicon in the silicon-rich oxide layer is much higher than in a silicon dioxide layer, bonds formed between a silicon atom and an oxygen atom in the silicon-rich oxide layer are much stronger. Consequently, the chance for an aluminum atom in the metallic layer to react with an oxygen atom in the silicon-rich oxide layer is greatly reduced. Hence, lattice vacancies/voids that can lead to conventional stress migration and thermal induced migration problems are prevented.

Abstract translation: 一种能够减少金属层内的内部应力的金属互连的制造方法。 该方法包括在形成金属层之前和之后形成富硅氧化物层的步骤。 因此，金属层被富硅氧化物层完全封闭，并且避免了金属层和任何二氧化硅层之间的任何直接接触。 由于富硅氧化物层中的硅量远高于二氧化硅层，所以富硅氧化物层中的硅原子和氧原子之间形成的键更强。 因此，金属层中的铝原子与富氧氧化物层中的氧原子反应的可能性大大降低。 因此，可以防止可能导致常规应力迁移和热诱导迁移问题的晶格空位/空隙。

公开(公告)号：US06225209B1

公开(公告)日：2001-05-01

申请号：US09150525

申请日：1998-09-10

Applicant: Yei-Hsiung Lin ,  Chih-Chun Huang ,  Chen-Bin Lin ,  Cheng-Hui Chung

Inventor： Yei-Hsiung Lin ,  Chih-Chun Huang ,  Chen-Bin Lin ,  Cheng-Hui Chung

IPC: H01L214763

CPC classification number: H01L21/02126 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/31625 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76828 ,  H01L21/823425 ,  H01L21/823475 ,  H01L29/665

Abstract: A method for fabricating a crack resistant inter-layer dielectric for a salicide process. The method includes forming an insulating layer on a provided substrate, forming a planarized inter-layer dielectric layer on the insulating layer, and performing a short-duration thermal treatment to increase the density of the inter-layer dielectric layer.

Abstract translation: 一种用于制造用于自对准硅化物工艺的耐裂纹层间电介质的方法。 该方法包括在所提供的衬底上形成绝缘层，在绝缘层上形成平坦化的层间电介质层，并进行短时间热处理以增加层间电介质层的密度。

公开(公告)号：US06242315B1

公开(公告)日：2001-06-05

申请号：US09186126

申请日：1998-11-04

Applicant: Chen-Bin Lin ,  Cheng-Hui Chung ,  Yei-Hsiung Lin ,  Ching-Chun Huang

Inventor： Chen-Bin Lin ,  Cheng-Hui Chung ,  Yei-Hsiung Lin ,  Ching-Chun Huang

IPC: H01L2120

CPC classification number: H01L28/55 ,  H01L21/76838 ,  H01L28/60

Abstract: A method of manufacturing the metallic electrodes of a capacitor in a mixed mode semiconductor device. The method comprises the steps of providing a substrate having a conductive layer and the lower electrode of a capacitor formed thereon, and then depositing a dielectric layer over the substrate. A first opening and a second opening are then formed in the dielectric layer. The first opening exposes a portion of the conductive layer while the second opening exposes a portion of the lower electrode. Finally, a conductive plug and the upper electrode of the capacitor are formed in the respective first and second openings that are in corresponding positions above the conductive layer and lower electrode, respectively.

Abstract translation: 一种在混合模式半导体器件中制造电容器的金属电极的方法。 该方法包括以下步骤：提供具有导电层和形成在其上的电容器的下电极的衬底，然后在衬底上沉积介电层。 然后在电介质层中形成第一开口和第二开口。 第一开口暴露导电层的一部分，而第二开口暴露下部电极的一部分。 最后，分别在导电层和下电极上方的相应位置的相应的第一和第二开口中形成导电插塞和电容器的上电极。

公开(公告)号：US6086951A

公开(公告)日：2000-07-11

申请号：US332342

申请日：1999-06-14

Applicant: Chen-Bin Lin ,  Cheng-Hui Chung ,  Yu-Ju Liu

Inventor： Chen-Bin Lin ,  Cheng-Hui Chung ,  Yu-Ju Liu

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/8242

CPC classification number: H01L28/55 ,  H01L28/60 ,  H01L21/76801 ,  H01L21/76838

Abstract: A method of forming metallic capacitor. The method includes forming a lower electrode for forming the capacitor and a metal conductive line over an inter-layer dielectric such that there are gaps between and on the sides of the lower electrode and the metal conductive line. Thereafter, a first oxide layer is formed that fills the gap, and then a second oxide layer is formed over the inter-layer dielectric. The second oxide layer is later patterned to form a cap oxide layer having an opening that exposes a portion of the lower electrode. Subsequently, a thin dielectric layer is formed over the lower electrode and the cap oxide layer. Finally, an upper electrode is formed over the thin dielectric layer filling the opening.

Abstract translation: 一种形成金属电容器的方法。 该方法包括形成用于形成电容器的下电极和在层间电介质上的金属导电线，使得在下电极和金属导线之间的两侧之间和之间存在间隙。 此后，形成填充间隙的第一氧化物层，然后在层间电介质上形成第二氧化物层。 随后将第二氧化物层图案化以形成具有暴露下部电极的一部分的开口的帽氧化物层。 随后，在下电极和盖氧化物层上形成薄介电层。 最后，在填充开口的薄介电层上形成上电极。