公开(公告)号：US5998269A

公开(公告)日：1999-12-07

申请号：US35139

申请日：1998-03-05

申请人： Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

发明人： Kuo-Ching Huang ,  Shou-Gwo Wuu ,  Jenn-Ming Huang ,  Dun-Nian Yaung

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8244 ,  H01L21/3215 ,  H01L21/335 ,  H01L21/74

CPC分类号： H01L27/11 ,  H01L21/28512 ,  H01L21/76895 ,  H01L29/66545

摘要： A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the semiconductor substrate to fill the gaps. The hard mask layer is removed. The polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted to form the buried contact. A refractory metal layer is deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines and planarized to form polycide gate electrodes and interconnection lines. The dielectric material layer is removed. An oxide layer is deposited and anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

摘要翻译： 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，其中它们不被掩模覆盖以形成多晶硅栅电极和互连线，其中间隙留在栅电极和互连线之间。 介电材料层沉积在半导体衬底上以填补间隙。 去除硬掩模层。 多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 植入离子以形成埋入的接触。 沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的难熔金属层并且被平坦化以形成多晶硅栅极电极和互连线。 去除介电材料层。 沉积氧化物层并各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US07037776B2

公开(公告)日：2006-05-02

申请号：US10323981

申请日：2002-12-19

申请人： Jenn-Ming Huang ,  Chen-Yong Lin

发明人： Jenn-Ming Huang ,  Chen-Yong Lin

IPC分类号： H01L21/8242

CPC分类号： H01L27/1104 ,  H01L27/10861 ,  H01L27/11

摘要： A method of fabricating a DRAM cell, comprising the following steps. A substrate is provided. An isolation structure is formed within the substrate. The substrate is patterned to form nodes adjacent the isolation structure. Doped regions are formed with the substrate adjacent the nodes. A gate dielectric layer is formed over the patterned substrate, lining the nodes. A conductive layer is formed over the gate dielectric layer, filling the nodes. The conductive layer is patterned to form: a top electrode capacitor within the nodes; and respective word lines over the substrate adjacent the top electrode capacitor; each word line having exposed side walls. Source/drain regions are formed adjacent the word lines.

摘要翻译： 一种制造DRAM单元的方法，包括以下步骤。 提供基板。 在衬底内形成隔离结构。 将衬底图案化以形成邻近隔离结构的节点。 掺杂区域与衬底相邻的节点形成。 栅极电介质层形成在图案化衬底上，衬在节点上。 导电层形成在栅介质层上，填充节点。 将导电层图案化以形成：节点内的顶部电极电容器; 以及邻近顶部电极电容器的衬底上的各个字线; 每个字线具有暴露的侧壁。 源极/漏极区域形成在字线附近。

公开(公告)号：US07030440B2

公开(公告)日：2006-04-18

申请号：US10894550

申请日：2004-07-20

申请人： Jenn-Ming Huang

发明人： Jenn-Ming Huang

IPC分类号： H01L27/108

CPC分类号： H01L27/10861 ,  H01L27/10867

摘要： A method for forming, within a double well formation, an array of DRAM memory cells isolated from each other by shallow trench isolation (STI), each cell comprising a MOSFET access transistor and a storage trench capacitor. A top plate of said capacitor is the trench wall within a deep N-well portion of the double well and the bottom plate is formed of a doped polysilicon layer within the trench, which layer is partially separated from the trench sidewalls by a dielectric layer whose upper portion is removed to allow the formation of a autodiffused doped channel between said polysilicon plate and the source region of the access transistor. The method uses a single dielectric layer deposition to serve as both a gate dielectric for the MOSFET and a capacitor dielectric and requires only a single deposition of polysilicon to serve as both the transistor gate electrode and a capacitor plate.

摘要翻译： 在双阱形成中形成通过浅沟槽隔离（STI）彼此隔离的DRAM存储单元的阵列的方法，每个单元包括MOSFET存取晶体管和存储沟槽电容器。 所述电容器的顶板是双阱的深N阱部分内的沟槽壁，并且底板由沟槽内的掺杂多晶硅层形成，该层通过电介质层与沟槽侧壁部分地分离， 去除上部部分以允许在所述多晶硅板和存取晶体管的源极区域之间形成自扩散掺杂沟道。 该方法使用单个电介质层沉积来用作MOSFET的栅极电介质和电容器电介质，并且仅需要单个沉积多晶硅来充当晶体管栅电极和电容器板。

公开(公告)号：US20050095856A1

公开(公告)日：2005-05-05

申请号：US10963324

申请日：2004-10-12

申请人： An-Chun Tu ,  Jenn-Ming Huang

发明人： An-Chun Tu ,  Jenn-Ming Huang

IPC分类号： F28C3/08 ,  F28D5/00 ,  F28F25/08 ,  H01L21/44

CPC分类号： F28D5/00 ,  F28C3/08 ,  F28F25/08

摘要： A novel sequence of process steps is provided for forming void-free interlevel dielectric layers between closely spaced gate electrodes. Closely spaced gate electrodes having sidewall spacers are formed on a substrate. After using the sidewall spacers to form self-aligned source/drain contacts and self-aligned silicide contacts, the sidewall spacers are removed. By removing the sidewall spacers, the aspect ratio of the gap between adjacent closely spaced gate electrodes is substantially reduced (from greater than 5 to less than 2), thereby preventing voids during the subsequent deposition of an ILD layer.

摘要翻译： 提供了一种新颖的工艺步骤序列，用于在紧密间隔的栅电极之间形成无空隙的层间电介质层。 在衬底上形成具有侧壁间隔物的紧密间隔开的栅电极。 在使用侧壁间隔件以形成自对准的源极/漏极触点和自对准硅化物触点之后，去除侧壁间隔物。 通过去除侧壁间隔物，相邻的紧密间隔的栅电极之间的间隙的纵横比显着减小（从大于5到小于2），从而防止在随后沉积ILD层期间的空隙。

公开(公告)号：US6159786A

公开(公告)日：2000-12-12

申请号：US210702

申请日：1998-12-14

申请人： Min-Hsiung Chiang ,  James Cheng-Ming Wu ,  Jenn-Ming Huang

发明人： Min-Hsiung Chiang ,  James Cheng-Ming Wu ,  Jenn-Ming Huang

IPC分类号： H01L21/3105 ,  H01L21/8242 ,  H01L21/8234 ,  H01L21/8244

CPC分类号： H01L27/10852 ,  H01L21/31055 ,  H01L27/10894

摘要： A new method of maintaining good control of the dielectric thickness over a top capacitor plate during planarization by CMP by introducing a CMP stop layer under the topmost dielectric layer is described. Semiconductor device structures, including a node contact region, are provided in and on a semiconductor substrate. A bottom plate electrode is formed contacting the node contact region through an opening in a first insulating layer. A capacitor dielectric layer is deposited overlying the bottom plate electrode. A second conducting layer is deposited overlying the capacitor dielectric to form a top plate electrode of the capacitor. A second insulating layer is deposited overlying the second conducting layer. A silicon nitride polish stop layer is deposited overlying the second insulating layer. The polish stop layer, second insulating layer, second conducting layer, and capacitor dielectric layer are patterned to form the DRAM integrated circuit device. A third insulating layer is deposited overlying the first insulating layer and the polish stop layer of the DRAM integrated circuit device. The third insulating layer is planarized by chemical mechanical polishing stopping at the polish stop layer. The polish stop layer protects the top capacitor plate from damage.

摘要翻译： 描述了在通过CMP平坦化期间在顶部电容器板上保持对电介质厚度的良好控制的新方法，其中在最下面的介电层下面引入CMP停止层。 包括节点接触区域的半导体器件结构被提供在半导体衬底中和半导体衬底上。 通过第一绝缘层中的开口形成接触节点接触区域的底板电极。 电容器电介质层沉积在底板电极上。 沉积在电容器电介质上的第二导电层以形成电容器的顶板电极。 沉积在第二导电层上的第二绝缘层。 沉积覆盖在第二绝缘层上的氮化硅抛光停止层。 对抛光停止层，第二绝缘层，第二导电层和电容器电介质层进行构图以形成DRAM集成电路器件。 沉积在DRAM集成电路器件的第一绝缘层和抛光停止层上的第三绝缘层。 通过在抛光停止层处的化学机械抛光停止将第三绝缘层平坦化。 抛光停止层保护顶部电容器板免受损坏。

公开(公告)号：US5963839A

公开(公告)日：1999-10-05

申请号：US986667

申请日：1997-12-08

申请人： Jenn-Ming Huang

发明人： Jenn-Ming Huang

IPC分类号： H01L21/285 ,  H01L21/31 ,  H01L21/44

CPC分类号： H01L21/28525

摘要： Making low resistance contact between two silicon layers has been accomplished by implanting nitrogen ions into a freshly formed silicon surface thereby forming a nitrogen rich layer at the surface which suppresses formation of a surface layer of oxide, the normal 20-30 Angstrom thick native oxide being now restricted to 3 or 4 Angstroms. When a layer of polysilicon is deposited onto this nitrided surface good, low resistance electrical contact is made. The process is fully compatible with existing methods for the manufacture of integrated circuits. An example of its application to making low resistance contact to a FET gate electrode is given.

摘要翻译： 通过将氮离子注入到新形成的硅表面中来实现两个硅层之间的低电阻接触，从而在表面形成富含氮的层，其抑制氧化物的表面层的形成，正常的20-30埃厚的自然氧化物是 现在限制在3或4埃。 当多晶硅层沉积在该氮化表面上时，具有低电阻的电接触。 该过程完全兼容现有的集成电路制造方法。 给出了其应用于向FET栅电极进行低电阻接触的示例。

公开(公告)号：US5726932A

公开(公告)日：1998-03-10

申请号：US663577

申请日：1996-06-13

申请人： Jin-Yuan Lee ,  Jenn-Ming Huang ,  Ming-Chih Chung

发明人： Jin-Yuan Lee ,  Jenn-Ming Huang ,  Ming-Chih Chung

IPC分类号： G11C11/412 ,  H01L27/11 ,  G11C11/00

CPC分类号： G11C11/412 ,  H01L27/1112 ,  Y10S257/903

摘要： An SRAM transistor cell on a doped semiconductor substrate comprises a first pass transistor and a second pass transistor, a first driver transistor and a second driver transistor and a saturated mode transistor. The device includes a first and second load resistor, first second and third nodes, a bit lines and interconnection lines. The first driver transistor drain region is connects to the first node. The control gate electrode cross connects via the first interconnection line to the second node. The second driver transistor drain region connects to the third node and the control gate electrode cross connects via the second interconnection line to the first node. The control gate electrodes of the pass transistors connect to a single input line. The drain region of the first pass transistor connects to the first node. The drain region of the second pass transistor connects to the second node. The source region of the first pass transistor connect to the bit line bar. The source region of the second pass transistor is connects to the bit line. The drain region and control gate electrode of the saturated mode transistor connect to the second node and the source region of the saturated mode transistor connects to the third node.

摘要翻译： 掺杂半导体衬底上的SRAM晶体管单元包括第一传输晶体管和第二传输晶体管，第一驱动晶体管和第二驱动晶体管以及饱和模式晶体管。 该器件包括第一和第二负载电阻器，第一和第三节点，位线和互连线。 第一驱动晶体管漏区连接到第一节点。 控制栅电极经由第一互连线交叉连接到第二节点。 第二驱动器晶体管漏极区域连接到第三节点，并且控制栅极电极经由第二互连线交叉连接到第一节点。 传输晶体管的控制栅电极连接到单个输入线。 第一级晶体管的漏极区连接到第一节点。 第二传输晶体管的漏极区域连接到第二节点。 第一级晶体管的源极区域连接到位线条。 第二传输晶体管的源极区域连接到位线。 饱和模式晶体管的漏极区域和控制栅电极连接到第二节点，饱和模式晶体管的源极区域连接到第三个节点。

公开(公告)号：US5494843A

公开(公告)日：1996-02-27

申请号：US496020

申请日：1995-06-28

申请人： Jenn-Ming Huang

发明人： Jenn-Ming Huang

IPC分类号： H01L21/8244 ,  H01L27/105 ,  H01L27/11 ,  H01L21/70

CPC分类号： H01L27/11 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/1116 ,  Y10S148/082

摘要： A method for fabricating CMOS chips, using a SRAM cell composed of, both NFET and PFET devices, or only NFETs, as well as incorporating NFET and PFET peripheral devices, is described. This process features an NFET, used in the SRAM cell, where a lightly doped arsenic source and drain region is used to achieve maximum device performance, in terms of saturation current, as well as gate to diffusion overlap capacitance. However the NFET used for the peripheral device is fabricated using a lightly doped phosphorous source and drain region, to allow for more protection against the deleterious hot carrier injection phenomena.

摘要翻译： 描述了使用由NFET和PFET器件或仅NFET组成的SRAM单元以及并入NFET和PFET外围器件来制造CMOS芯片的方法。 该工艺的特征是在SRAM单元中使用的NFET，其中使用轻掺杂砷源极和漏极区域来实现饱和电流以及栅极扩散重叠电容的最大器件性能。 然而，用于外围器件的NFET使用轻掺杂的磷源极和漏极区制造，以允许针对有害热载流子注入现象的更多保护。