公开(公告)号：US20200320017A1

公开(公告)日：2020-10-08

申请号：US16374952

申请日：2019-04-04

Applicant: Cisco Technology, Inc.

Inventor： Ravikiran Kaidala Lakshman ,  Tanjore K. Suresh ,  Deepak Srinivas Mayya ,  Sagar Borikar

IPC: G06F12/1081 ,  H04L12/861 ,  G06F12/1036 ,  H04L12/879

Abstract: Presented herein are techniques enable existing hardware input/output resources, such as the hardware queues (queue control registers), of a network interface card to be shared with different hosts (i.e., each queue mapped to many hosts) by logically segregating the hardware I/O resources using assignable interfaces each associated with a distinct Process Address Space Identifier (PASID). That is, different assignable interfaces are created and associated with different PASIDs, and these assignable interfaces each correspond to a different host (i.e., there is a mapping between a host, an assignable interface, a PASID, and a partition of a hardware queue). The result is that that the hosts can use the assignable interface to directly access the hardware queue partition that corresponds thereto.

公开(公告)号：US10114792B2

公开(公告)日：2018-10-30

申请号：US14853598

申请日：2015-09-14

Applicant: CISCO TECHNOLOGY, INC.

Inventor： Prabhath Sajeepa ,  Sagar Borikar

IPC: G06F15/167 ,  G06F15/173

Abstract: An example method for facilitating low latency remote direct memory access (RDMA) for microservers is provided and includes generating queue pair (QPs) in a memory of an input/output (I/O) adapter of a microserver chassis having a plurality of compute nodes executing thereon, the QPs being associated with a remote direct memory access (RDMA) connection between a first compute node and a second compute node in the microserver chassis, setting a flag in the QPs to indicate that the RDMA connection is local to the microserver chassis, and performing a loopback of RDMA packets within the I/O adapter from one memory region in the I/O adapter associated with the first compute node of the RDMA connection to another memory region in the I/O adapter associated with the second compute node of the RDMA connection.

公开(公告)号：US10114764B2

公开(公告)日：2018-10-30

申请号：US15910846

申请日：2018-03-02

Applicant: CISCO TECHNOLOGY, INC.

Inventor： Sagar Borikar

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/109 ,  G06F3/06 ,  G06F12/10

Abstract: An example method for facilitating multi-level paging and address translation in a network environment is provided and includes receiving a request for memory in a physical memory of a network element, associating the request with a first virtual address space, mapping a memory region located in the physical memory to a first window in the first virtual address space, the memory region being also mapped to a second window in a different, second virtual address space, remapping the first window in the first virtual address space to the second window in the second virtual address space, and responding to the request with addresses of the second window in the second virtual address space.

公开(公告)号：US20180189191A1

公开(公告)日：2018-07-05

申请号：US15910846

申请日：2018-03-02

Applicant: CISCO TECHNOLOGY, INC.

Inventor： Sagar Borikar

IPC: G06F12/109 ,  G06F3/06 ,  G06F12/10

CPC classification number: G06F12/109 ,  G06F3/0605 ,  G06F3/0631 ,  G06F3/067 ,  G06F12/10 ,  G06F12/1072 ,  G06F2212/1016 ,  G06F2212/154 ,  G06F2212/65 ,  G06F2212/651 ,  G06F2212/657

Abstract: An example method for facilitating multi-level paging and address translation in a network environment is provided and includes receiving a request for memory in a physical memory of a network element, associating the request with a first virtual address space, mapping a memory region located in the physical memory to a first window in the first virtual address space, the memory region being also mapped to a second window in a different, second virtual address space, remapping the first window in the first virtual address space to the second window in the second virtual address space, and responding to the request with addresses of the second window in the second virtual address space.

公开(公告)号：US20170054593A1

公开(公告)日：2017-02-23

申请号：US14831894

申请日：2015-08-21

Applicant: CISCO TECHNOLOGY, INC.

Inventor： Sagar Borikar ,  Prabhath Sajeepa

IPC: H04L12/24 ,  H04L12/931

CPC classification number: H04L49/35 ,  H04L41/0816 ,  H04L41/12

Abstract: An example method for transformation of Peripheral Component Interconnect Express (PCIe) compliant virtual devices in a server in a network environment is provided and includes receiving, during runtime of the server, a request to change a first configuration of a PCIe compliant virtual device to a different second configuration, identifying a bridge on a PCIe topology below which the virtual device is located, issuing a simulated secondary bus reset to the bridge, the virtual device being reconfigured according to the change in configuration after the simulated secondary bus reset is issued, re-enumerating below the bridge after the change in configuration completes without rebooting the server, and updating the PCI topology with the virtual device in the second configuration. A virtual interface card adapter traps the simulated secondary bus reset, removes the virtual device from the PCI topology, and reconfigures the virtual device from the first configuration to the second configuration.

Abstract translation: 提供了用于在网络环境中在服务器中变换外围组件互连Express（PCIe）兼容虚拟设备的示例性方法，并且包括在服务器运行时期间接收将PCIe兼容虚拟设备的第一配置更改为 不同的第二配置，识别虚拟设备所在的PCIe拓扑下的桥接器，向桥接器发出模拟次级总线复位，根据模拟次级总线复位发生后的配置变化重新配置虚拟设备 在组态更改完成后，在桥下方枚举，而不重新启动服务器，并在第二个配置中使用虚拟设备更新PCI拓扑。 虚拟接口卡适配器捕获模拟辅助总线复位，从PCI拓扑中删除虚拟设备，并将虚拟设备从第一个配置重新配置到第二个配置。

公开(公告)号：US20230116820A1

公开(公告)日：2023-04-13

申请号：US17751210

申请日：2022-05-23

Applicant: Cisco Technology, Inc.

Inventor： Ayan Banerjee ,  Ramesh Sivakolundu ,  Chakradhar Kar ,  Sagar Borikar ,  Anant Thakar

IPC: H04L47/72 ,  H04L67/141

Abstract: Techniques for sending Compute Express Link (CXL) packets over Ethernet (CXL-E) in a composable data center that may include disaggregated, composable servers. The techniques may include receiving, from a first server device, a request to bind the first server device with a multiple logical device (MLD) appliance. Based at least in part on the request, a first CXL-E connection may be established for the first server device to export a computing resource to the MLD appliance. The techniques may also include receiving, from the MLD appliance, an indication that the computing resource is available, and receiving, from a second server device, a second request for the computing resource. Based at least in part on the second request, a second CXL-E connection may be established for the second server device to consume or otherwise utilize the computing resource of the first server device via the MLD appliance.

公开(公告)号：US11336581B2

公开(公告)日：2022-05-17

申请号：US16887775

申请日：2020-05-29

Applicant: Cisco Technology, Inc.

Inventor： Sagar Borikar ,  John William Marshall

IPC: H04L12/841 ,  H04L12/801 ,  H04L29/06 ,  H04L12/861 ,  H04L47/28 ,  H04L47/11 ,  H04L69/22 ,  H04L49/90

Abstract: A method is provided by which a network adapter device receives a packet sent over a network from a peer, the packet including an enqueue timestamp indicating when the packet has been enqueued at the network adapter device. The network adapter device parses a header of the packet to detect whether the header includes bits indicating that the peer device is experiencing congestion, and obtains packet metadata of the packet and the enqueue timestamp of the packet. The network adapter device compares the packet metadata with information in a flow table to identify an entry in the flow table corresponding to a flow to which the packet metadata matches. The network adapter device sets a timer associated with the flow, the timer for use in scheduling transmission of a next packet provided by the host to be sent to the peer.

公开(公告)号：US10929310B2

公开(公告)日：2021-02-23

申请号：US16290101

申请日：2019-03-01

Applicant: Cisco Technology, Inc.

Inventor： Sagar Borikar ,  Ravikiran Kaidala Lakshman

IPC: G06F12/1081 ,  G06F12/12 ,  G06F13/12

Abstract: Systems and methods provide for optimizing utilization of an Address Translation Cache (ATC). A network interface controller (NIC) can write information reserving one or more cache lines in a first level of the ATC to a second level of the ATC. The NIC can receive a request for a direct memory access (DMA) to an untranslated address in memory of a host computing system. The NIC can determine that the untranslated address is not cached in the first level of the ATC. The NIC can identify a selected cache line in the first level of the ATC to evict using the request and the second level of the ATC. The NIC can receive a translated address for the untranslated address. The NIC can cache the untranslated address in the selected cache line. The NIC can perform the DMA using the translated address.

公开(公告)号：US10585830B2

公开(公告)日：2020-03-10

申请号：US15869256

申请日：2018-01-12

Applicant: Cisco Technology, Inc.

Inventor： Prabhath Sajeepa ,  Sagar Borikar

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16 ,  G06F13/24

Abstract: An example method for facilitating policy-driven storage in a microserver computing environment is provided and includes receiving, at an input/output (I/O) adapter in a microserver chassis having a plurality of compute nodes and a shared storage resource, policy contexts prescribing storage access parameters of respective compute nodes and enforcing the respective policy contexts on I/O operations by the compute nodes, in which respect a particular I/O operation by any compute node is not executed if the respective policy context does not allow the particular I/O operation. The method further includes allocating tokens to command descriptors associated with I/O operations for accessing the shared storage resource, identifying a violation of any policy context of any compute node based on availability of the tokens, and throttling I/O operations by other compute nodes until the violation disappears.

公开(公告)号：US20200021532A1

公开(公告)日：2020-01-16

申请号：US16031127

申请日：2018-07-10

Applicant: Cisco Technology, Inc.

Inventor： Sagar Borikar ,  John William Marshall

IPC: H04L12/841 ,  H04L12/861 ,  H04L29/06 ,  H04L12/801

Abstract: A method is provided by which a network adapter device receives a packet sent over a network from a peer, the packet including an enqueue timestamp indicating when the packet has been enqueued at the network adapter device. The network adapter device parses a header of the packet to detect whether the header includes bits indicating that the peer device is experiencing congestion, and obtains packet metadata of the packet and the enqueue timestamp of the packet. The network adapter device compares the packet metadata with information in a flow table to identify an entry in the flow table corresponding to a flow to which the packet metadata matches. The network adapter device sets a timer associated with the flow, the timer for use in scheduling transmission of a next packet provided by the host to be sent to the peer.