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公开(公告)号：US20210248506A1
公开(公告)日：2021-08-12
申请号：US17054284
申请日：2019-05-06
Applicant: D-WAVE SYSTEMS INC.
Inventor： Emile M. Hoskinson , Reuble Mathew
Abstract: Devices, systems, and methods that include a qubit coupled to a projective-source digital-to-analog converter (PSDAC) for projective measurement of the qubit. A change in flux state of the PSDAC from a first flux state to a second flux state generates a fast-flux step or fast-step waveform that can be applied to the qubit to perform projective measurement of the qubit. For a quantum processor that includes a set of qubits wherein each qubit is coupled to a respective PSDAC, a shared trigger line can activate each PSDAC to generate a respective fast-flux step or fast-step waveform. Synchronization devices can synchronize the fast-flux steps or fast-step waveforms, allowing for projective readout of the set of qubits.
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12.发明授权公开(公告)号：US11730066B2
公开(公告)日：2023-08-15
申请号：US17399375
申请日：2021-08-11
Applicant: D-WAVE SYSTEMS INC.
Inventor： Mark W. Johnson , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Kelly T. R. Boothby , Loren J. Swenson , Emile M. Hoskinson , Christopher B. Rich , Jan E. S. Johansson
CPC classification number: H10N60/124 , G06N10/00 , H10N60/805
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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公开(公告)号：US11681940B2
公开(公告)日：2023-06-20
申请号：US17379172
申请日：2021-07-19
Applicant: D-WAVE SYSTEMS INC.
Inventor： Andrew Douglas King , Alexandre Fréchette , Evgeny A. Andriyash , Trevor Michael Lanting , Emile M. Hoskinson , Mohammad H. Amin
IPC: G06N10/00 , G06F15/163
CPC classification number: G06N10/00 , G06F15/163
Abstract: Degeneracy in analog processor (e.g., quantum processor) operation is mitigated via use of floppy qubits or domains of floppy qubits (i.e., qubit(s) for which the state can be flipped with no change in energy), which can significantly boost hardware performance on certain problems, as well as improve hardware performance for more general problem sets. Samples are drawn from an analog processor, and devices comprising the analog processor evaluated for floppiness. A normalized floppiness metric is calculated, and an offset added to advance the device in annealing. Degeneracy in a hybrid computing system that comprises a quantum processor is mitigated by determining a magnetic susceptibility of a qubit, and tuning a tunneling rate for the qubit based on a tunneling rate offset determined based on the magnetic susceptibility. Quantum annealing evolution is controlled by causing the evolution to pause for a determined pause duration.
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公开(公告)号：US20230027682A1
公开(公告)日：2023-01-26
申请号：US17786192
申请日：2020-12-15
Applicant: D-WAVE SYSTEMS INC.
Inventor： Reza Molavi , Mark H. Volkmann , Emile M. Hoskinson , Richard G. Harris , Trevor M. Lanting , Paul I. Bunyk , Andrew J. Berkley
Abstract: An analog computing system having a qubit which is provided with inductors positioned near to the qubit's Josephson junctions and inductors positioned far from the qubit's Josephson junctions. The near inductors exhibit capacitance-reducing behavior and the far inductors exhibit capacitance-increasing behavior as their respective inductances are increased. Near and far inductors can be tuned to homogenize the capacitance of the qubit across a range of programmable states based on predicted and target capacitance for the qubit. The inductors may be tuned to homogenize both capacitance and inductance.
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公开(公告)号：US11295225B2
公开(公告)日：2022-04-05
申请号：US16029026
申请日：2018-07-06
Applicant: D-Wave Systems Inc.
Inventor： Emile M. Hoskinson , Trevor Michael Lanting
Abstract: Passive and actives approaches to mitigating the effects of spin-bath polarization are described and illustrated. Such may, for example, include at least partially depolarizing the spin-bath polarization, for instance by: performing an annealing cycle by the quantum processor to generate a final state of a qubit of the quantum processor; flipping the final state of the qubit of the quantum processor to an opposite state; and latching the qubit in the opposite state for a predetermined duration.
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Patent Agency Ranking
公开(公告)号：US20210190885A1
公开(公告)日：2021-06-24
申请号：US17054631
申请日：2019-05-16
Applicant: D-WAVE SYSTEMS INC.
Inventor： Loren J. Swenson , Emile M. Hoskinson , Mark H. Volkmann , Andrew J. Berkley , George E.G. Sterling , Jed D. Whittaker
IPC: G01R33/035 , H01L39/22 , G06N10/00
Abstract: Superconducting integrated circuits may advantageously employ superconducting resonators coupled to a microwave transmission line to efficiently address superconducting flux storage devices. In an XY-addressing scheme, a global flux bias may be applied to a number of superconducting flux storage devices via a low-frequency address line, and individual superconducting flux storage devices addressed via application of high-frequency pulses via resonators driven by the microwave transmission line. Frequency multiplexing can be employed to provide signals to two or more resonators. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to provide Z-addressing. A low-frequency current bias may be combined with a high-frequency current in one or more superconducting resonators to eliminate a flux bias line. A low-frequency current bias may be used at room temperature to identify the presence of a DC short, an open, and/or an unexpected resistance in a superconducting resonator.
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公开(公告)号：US20190228331A1
公开(公告)日：2019-07-25
申请号：US16258082
申请日：2019-01-25
Applicant: D-WAVE SYSTEMS INC.
Inventor： Richard G. Harris , Paul I. Bunyk , Mohammad H.S. Amin , Emile M. Hoskinson
Abstract: In a quantum processor some couplers couple a given qubit to a nearest neighbor qubit (e.g., vertically and horizontally in an ordered 2D array), other couplers couple to next-nearest neighbor qubits (e.g., diagonally in the ordered 2D array). Couplers may include half-couplers, to selectively provide communicative coupling between a given qubit and other qubits, which may or may not be nearest or even next-nearest-neighbors. Tunable couplers selective mediate communicative coupling. A control system may impose a connectivity on a quantum processor, different than an “as designed” or “as manufactured” physical connectivity. Imposition may be via a digital processor processing a working or updated working graph, to map or embed a problem graph. A set of exclude qubits may be created from a comparison of hardware and working graphs. An annealing schedule may adjust a respective normalized inductance of one or more qubits, for instance to exclude certain qubits.
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公开(公告)号：US20250053842A1
公开(公告)日：2025-02-13
申请号：US18718588
申请日：2022-12-14
Applicant: D-WAVE SYSTEMS INC.
Inventor： Emile M. Hoskinson
Abstract: In a superconducting quantum processor, inductance is a characteristic of superconducting flux qubits and used to achieve coupling between qubits. In general, higher qubit energy scale results in better quantum processor performance. Energy scale of qubits can be increased by reducing inductance. For each Ising spin problem, qubit energy scale can be increased by determining the unused inductance-tuner range for each qubit and the minimum homogenized inductance achievable across all qubits, then adjusting the inductance-tuner to achieve the minimum homogenized inductance. When the inductance of a qubit is changed, there is a shift in the CCJJ bias at which quantum annealing is performed for that qubit. The variation in CCJJ bias shift can be compensated by computing the shift in CCJJ bias due to the applied inductance and applying a compensating CCJJ bias via the CCJJ offset DAC.
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19.发明申请公开(公告)号：US20210013391A1
公开(公告)日：2021-01-14
申请号：US16098801
申请日：2017-05-03
Applicant: D-WAVE SYSTEMS INC.
Inventor： Mark W. Johnson , Paul I. Bunyk , Andrew J. Berkley , Richard G. Harris , Kelly T. R. Boothby , Loren J. Swenson , Emile M. Hoskinson , Christopher B. Rich , Jan E.S. Johansson
Abstract: Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
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公开(公告)号：US20190019099A1
公开(公告)日：2019-01-17
申请号：US16029026
申请日：2018-07-06
Applicant: D-Wave Systems Inc.
Inventor： Emile M. Hoskinson , Trevor Michael Lanting
Abstract: Passive and actives approaches to mitigating the effects of spin-bath polarization are described and illustrated. Such may, for example, include at least partially depolarizing the spin-bath polarization, for instance by: performing an annealing cycle by the quantum processor to generate a final state of a qubit of the quantum processor; flipping the final state of the qubit of the quantum processor to an opposite state; and latching the qubit in the opposite state for a predetermined duration.
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