公开(公告)号：US20110241157A1

公开(公告)日：2011-10-06

申请号：US12793515

申请日：2010-06-03

申请人： Carlos Mazure ,  Richard Ferrant ,  Konstantin Bourdelle ,  Bich-Yen Nguyen

发明人： Carlos Mazure ,  Richard Ferrant ,  Konstantin Bourdelle ,  Bich-Yen Nguyen

IPC分类号： H01L21/762 ,  H01L29/02

CPC分类号： H01L21/76254 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/76251

摘要： The invention relates to a method for manufacturing a semiconductor substrate, in particular a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor and the handle substrate to obtain a donor-handle compound.

摘要翻译： 本发明涉及一种制造半导体衬底，特别是绝缘体上半导体衬底的方法，该衬底通过提供施主衬底和处理衬底，形成典型地在手柄衬底内的一个或多个掺杂区域的图案， 通过分子键合供体和手柄底物以获得供体 - 处理化合物。

公开(公告)号：US07994560B2

公开(公告)日：2011-08-09

申请号：US12173702

申请日：2008-07-15

申请人： Christian Caillat ,  Richard Ferrant

发明人： Christian Caillat ,  Richard Ferrant

IPC分类号： H01L29/94

CPC分类号： H01L27/10823 ,  H01L27/0218 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/1203

摘要： An integrated circuit includes a substrate and at least one active region. A transistor produced in the active region separated from the substrate. This transistor includes a source or drain first region and a drain or source second region which are connected by a channel. A gate structure is position on top of said channel and operates to control the channel. The gate structure is formed in a trench whose sidewalls have a shape which converges (narrows) in the width dimension towards the substrate. A capacitor is also formed having a first electrode, a second electrode and a dielectric layer between the electrodes. This capacitor is also formed in a trench. An electrode line is connected to the first electrode of the capacitor. The second electrode of the capacitor is formed in a layer shared in common with at least part of the drain or source second region of the transistor. A bit line is located beneath the gate structure. The integrated circuit may, for example, be a DRAM memory cell.

摘要翻译： 集成电路包括衬底和至少一个有源区。 在与基板分离的有源区中产生的晶体管。 该晶体管包括源极或漏极第一区域以及通过沟道连接的漏极或源极第二区域。 栅极结构位于所述通道的顶部并且用于控制通道。 栅极结构形成在其侧壁具有朝向衬底的宽度尺寸收敛（窄））的形状的沟槽中。 电容器也形成为具有在电极之间的第一电极，第二电极和电介质层。 该电容器也形成在沟槽中。 电极线连接到电容器的第一电极。 电容器的第二电极形成在与晶体管的漏极或源极第二区域的至少一部分共同共享的层中。 位线位于门结构下方。 集成电路例如可以是DRAM存储单元。

公开(公告)号：US20110133822A1

公开(公告)日：2011-06-09

申请号：US13013580

申请日：2011-01-25

申请人： Carlos Mazure ,  Richard Ferrant

发明人： Carlos Mazure ,  Richard Ferrant

IPC分类号： G05F1/10 ,  H01L27/105 ,  G06F17/50

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/11807 ,  H01L27/1203

摘要： This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate defined by a pattern defining at least one field-effect transistor having: in the thin film of the SeOI substrate, a source region, a drain region, a channel region, and a front control gate region formed above the channel region; and in the base substrate beneath the buried oxide of the SeOI substrate, a back control gate region, arranged under the channel region and configured to shift the threshold voltage of the transistor in response to bias voltages. This invention also provides patterns defining standard-cell-type circuit structures and data-path-cell type circuit structures that include arrays of the FET patterns provided by this invention. Such circuit structures also include back gate lines connecting the back gate control regions. This invention also provides methods of operating and designing such semiconductor device structures.

摘要翻译： 本发明提供了一种半导体器件结构，其形成在传统的绝缘体上半导体（SeOI）衬底上，该衬底由限定至少一个场效应晶体管的图案限定，该场效应晶体管具有：在SeOI衬底的薄膜中，源极区， ，沟道区和形成在沟道区上方的前控制栅区; 以及位于所述SeOI衬底的所述掩埋氧化物之下的所述基底衬底中，所述背面控制栅极区域布置在所述沟道区域下方并且被配置为响应于偏压而移位所述晶体管的阈值电压。 本发明还提供了定义包括由本发明提供的FET图案的阵列的标准单元型电路结构和数据路径单元型电路结构的图案。 这种电路结构还包括连接背栅极控制区域的后栅极线。 本发明还提供了操作和设计这种半导体器件结构的方法。

公开(公告)号：US06995997B2

公开(公告)日：2006-02-07

申请号：US10862057

申请日：2004-06-04

申请人： Richard Ferrant

发明人： Richard Ferrant

IPC分类号： G11C15/00

CPC分类号： G11C15/04

摘要： A CAM cell with masking made in the form of an integrated circuit, including a first storage cell including a first transistor, first and second inverters in anti-parallel, and a second transistor; a comparison cell, including third and fourth transistors controlling a fifth transistor, connected in series with a sixth inhibiting transistor to a result line; and a second storage cell, including a seventh transistor in series with two inverters in anti-parallel and an eighth transistor, the second storage cell controlling the inhibiting transistor. The first, second, seventh, and eighth transistors may be N-channel transistors, and the third, fourth, fifth, and sixth transistors may be P-channel transistors.

摘要翻译： 具有以集成电路形式形成的掩蔽的CAM单元，包括：第一存储单元，包括第一晶体管，反并联的第一和第二反相器以及第二晶体管; 比较单元，包括控制第五晶体管的第三和第四晶体管，与第六抑制晶体管串联连接到结果行; 以及第二存储单元，其包括与反并联的两个反相器串联的第七晶体管和第八晶体管，所述第二存储单元控制所述抑制晶体管。 第一，第二，第七和第八晶体管可以是N沟道晶体管，并且第三，第四，第五和第六晶体管可以是P沟道晶体管。

公开(公告)号：US20050174873A1

公开(公告)日：2005-08-11

申请号：US11096970

申请日：2005-04-01

申请人： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

发明人： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

IPC分类号： G11C20060101 ,  G11C8/00 ,  G11C11/00 ,  G11C11/404 ,  G11C11/406 ,  G11C11/4097

CPC分类号： G11C11/404 ,  G11C7/18 ,  G11C8/08 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4097 ,  G11C2211/4016 ,  G11C2211/4065 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

公开(公告)号：US20050157534A1

公开(公告)日：2005-07-21

申请号：US10627955

申请日：2003-07-25

申请人： Richard Ferrant ,  Francois Jacquet

发明人： Richard Ferrant ,  Francois Jacquet

IPC分类号： G11C11/406 ,  G11C11/24

CPC分类号： G11C11/406

摘要： A DRAM including an array of storage elements arranged in lines and columns, and for each column: write means adapted to biasing at least a selected one of the elements to a charge level chosen from among a first predetermined high level and a second predetermined low level, combined with read circuitry adapted to determining whether the stored charge level is greater or smaller than a predetermined charge level; and isolation circuitry adapted to isolating the array from the read and/or write means, each column further including refreshment means, distinct from the read and write circuit, for increasing, beyond the first and second predetermined levels, the charge stored in a storage element.

摘要翻译： 一种DRAM，包括排列成行和列的存储元件的阵列，并且用于每列：写入装置，其适于将至少一个所选元素偏置到从第一预定高电平和第二预定低电平中选择的电荷电平 与读取电路组合，适于确定所存储的电荷电平是否大于或小于预定电荷电平; 以及隔离电路，其适于将阵列与读取和/或写入装置隔离，每列还包括与读取和写入电路不同的刷新装置，用于在第一和第二预定级别之外增加存储在存储元件中的电荷 。

公开(公告)号：US06920075B2

公开(公告)日：2005-07-19

申请号：US10450803

申请日：2001-12-14

申请人： Richard Ferrant

发明人： Richard Ferrant

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C7/00

CPC分类号： G11C11/4091 ,  G11C7/062 ,  G11C7/1006

摘要： The invention concerns an amplifier (1), capable of being controlled by an activation signal, for reading storage cells of a crossbar network comprising, for each column, a direct bit line (BLdi) and a reference bit line (BLri), the amplifier being common to two columns and producing an OR-Exclusive type combination of the states of the cells read in said two columns.

摘要翻译： 本发明涉及一种能够被激活信号控制的放大器（1），用于读取交叉开关网络的存储单元，其包括针对每列的直接位线（BLdi）和参考位线（BLri），放大器 对于两列是共同的，并且产生在所述两列中读取的单元的状态的OR-Exclusive类型组合。

公开(公告)号：US20050013163A1

公开(公告)日：2005-01-20

申请号：US10829877

申请日：2004-04-22

申请人： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

发明人： Richard Ferrant ,  Serguei Okhonin ,  Eric Carman ,  Michel Bron

IPC分类号： G11C11/404 ,  G11C16/04 ,  G11C16/28 ,  H01L20060101 ,  H01L27/108

CPC分类号： G11C16/28 ,  G11C11/404 ,  G11C2211/4013 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L29/7841

摘要： There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory cell and technique of reading data from and writing data into that memory cell. In this regard, in one embodiment of this aspect of the invention, the memory cell includes two transistors which store complementary data states. That is, the two-transistor memory cell includes a first transistor that maintains a complementary state relative to the second transistor. As such, when programmed, one of the transistors of the memory cell stores a logic low (a binary “0”) and the other transistor of the memory cell stores a logic high (a binary “1”). The data state of the two-transistor complementary memory cell may be read and/or determined by sampling, sensing measuring and/or detecting the polarity of the logic states stored in each transistor of complementary memory cell. That is, the two-transistor complementary memory cell is read by sampling, sensing measuring and/or detecting the difference in signals (current or voltage) stored in the two transistors.

摘要翻译： 这里描述和说明了许多发明。 在第一方面，本发明涉及从该存储单元读取数据并将数据写入该存储单元的存储单元和技术。 在这方面，在本发明的这个方面的一个实施例中，存储单元包括存储互补数据状态的两个晶体管。 也就是说，双晶体管存储单元包括相对于第二晶体管保持互补状态的第一晶体管。 这样，当被编程时，存储单元的一个晶体管存储逻辑低（二进制“0”），并且存储单元的另一晶体管存储逻辑高（二进制“1”）。 可以通过采样，感测测量和/或检测存储在互补存储器单元的每个晶体管中的逻辑状态的极性来读取和/或确定双晶体管互补存储单元的数据状态。 也就是说，通过采样，感测测量和/或检测存储在两个晶体管中的信号（电流或电压）的差异来读取双晶体管互补存储单元。

公开(公告)号：US06535987B1

公开(公告)日：2003-03-18

申请号：US09364151

申请日：1999-07-30

申请人： Richard Ferrant

发明人： Richard Ferrant

IPC分类号： G06F104

CPC分类号： H04L25/0272 ,  H04L25/029 ,  H04L25/0292 ,  H04L25/08

摘要： The present invention relates to an amplifier having a fan-out which varies according to the time spent between an edge of a propagation signal and an edge of a logic input signal, the amplifier including several identical blocks, each block having an output stage connected between a data input and a data output, the data input and output being respectively connected to the data inputs and outputs of the other blocks; a delay element, the delay elements of all blocks being connected in series, the delay element of the first block receiving the synchronization signal; an edge detector, the input of which is connected to the input of the output stage; and means for inhibiting the propagation of the synchronization signal through the delay element when the signal generated by the edge detector of the preceding block is active and for activating the output stage and the edge detector when the signal generated by the delay element of the preceding block is active.

摘要翻译： 本发明涉及一种放大器，其具有根据在传播信号的边缘和逻辑输入信号的边缘之间消耗的时间而变化的扇出，放大器包括几个相同的块，每个块的输出级连接在 数据输入和数据输出，数据输入和输出分别连接到其他块的数据输入和输出; 延迟元件，所有块的延迟元件串联连接，第一块的延迟元件接收同步信号; 边缘检测器，其输入端连接到输出级的输入端; 以及用于当由前一块的边缘检测器产生的信号有效时禁止同步信号通过延迟元件传播的装置，并且用于当由前一个块的延迟元件产生的信号激活时输出级和边缘检测器 活跃。

公开(公告)号：US06489810B2

公开(公告)日：2002-12-03

申请号：US09891964

申请日：2001-06-26

申请人： Richard Ferrant

发明人： Richard Ferrant

IPC分类号： H03K19007

CPC分类号： G11C17/16 ,  G11C17/18

摘要： An electronic circuit with digital output including an auto-stable assembly of latches (1), a control assembly (2), a blowable assembly (3), a logic gate (4) including a first input connected to a common point (14) between the auto-stable assembly (1) and the blowable assembly (3), and a second input connected to the control input (20) of the electronic circuit. A breaker (5) is controlled by the output of the logic gate (4) and arranged between the auto-stable assembly (1) and ground, and an associated process.

摘要翻译： 一种具有数字输出的电子电路，包括闩锁（1），控制组件（2），可吹塑组件（3），连接到公共点（14）的第一输入的逻辑门（4））的自动稳定组件， 在自动稳定组件（1）和可吹塑组件（3）之间，以及连接到电子电路的控制输入（20）的第二输入。 断路器（5）由逻辑门（4）的输出控制并且布置在自动稳定组件（1）和地之间，以及相关联的过程。