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    Integrated circuit comprising a transistor and a capacitor, and fabrication method
    1.
    发明授权
    Integrated circuit comprising a transistor and a capacitor, and fabrication method 有权
    包括晶体管和电容器的集成电路及其制造方法

    公开(公告)号：US07994560B2

    公开(公告)日：2011-08-09

    申请号：US12173702

    申请日：2008-07-15

    申请人： Christian Caillat ,  Richard Ferrant

    发明人： Christian Caillat ,  Richard Ferrant

    IPC分类号： H01L29/94

    CPC分类号： H01L27/10823 ,  H01L27/0218 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/1203

    摘要： An integrated circuit includes a substrate and at least one active region. A transistor produced in the active region separated from the substrate. This transistor includes a source or drain first region and a drain or source second region which are connected by a channel. A gate structure is position on top of said channel and operates to control the channel. The gate structure is formed in a trench whose sidewalls have a shape which converges (narrows) in the width dimension towards the substrate. A capacitor is also formed having a first electrode, a second electrode and a dielectric layer between the electrodes. This capacitor is also formed in a trench. An electrode line is connected to the first electrode of the capacitor. The second electrode of the capacitor is formed in a layer shared in common with at least part of the drain or source second region of the transistor. A bit line is located beneath the gate structure. The integrated circuit may, for example, be a DRAM memory cell.

    摘要翻译： 集成电路包括衬底和至少一个有源区。 在与基板分离的有源区中产生的晶体管。 该晶体管包括源极或漏极第一区域以及通过沟道连接的漏极或源极第二区域。 栅极结构位于所述通道的顶部并且用于控制通道。 栅极结构形成在其侧壁具有朝向衬底的宽度尺寸收敛（窄））的形状的沟槽中。 电容器也形成为具有在电极之间的第一电极，第二电极和电介质层。 该电容器也形成在沟槽中。 电极线连接到电容器的第一电极。 电容器的第二电极形成在与晶体管的漏极或源极第二区域的至少一部分共同共享的层中。 位线位于门结构下方。 集成电路例如可以是DRAM存储单元。

    INTEGRATED CIRCUIT COMPRISING A TRANSISTOR AND A CAPACITOR, AND FABRICATION METHOD
    2.
    发明申请
    INTEGRATED CIRCUIT COMPRISING A TRANSISTOR AND A CAPACITOR, AND FABRICATION METHOD 有权
    包含晶体管和电容器的集成电路，以及制造方法

    公开(公告)号：US20090121269A1

    公开(公告)日：2009-05-14

    申请号：US12173702

    申请日：2008-07-15

    申请人： Christian Caillat ,  Richard Ferrant

    发明人： Christian Caillat ,  Richard Ferrant

    IPC分类号： H01L27/108 ,  H01L21/8242

    CPC分类号： H01L27/10823 ,  H01L27/0218 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/1203

    摘要： An integrated circuit includes a substrate and at least one active region. A transistor produced in the active region separated from the substrate. This transistor includes a source or drain first region and a drain or source second region which are connected by a channel. A gate structure is position on top of said channel and operates to control the channel. The gate structure is formed in a trench whose sidewalls have a shape which converges (narrows) in the width dimension towards the substrate. A capacitor is also formed having a first electrode, a second electrode and a dielectric layer between the electrodes. This capacitor is also formed in a trench. An electrode line is connected to the first electrode of the capacitor. The second electrode of the capacitor is formed in a layer shared in common with at least part of the drain or source second region of the transistor. A bit line is located beneath the gate structure. The integrated circuit may, for example, be a DRAM memory cell.

    摘要翻译： 集成电路包括衬底和至少一个有源区。 在与基板分离的有源区中产生的晶体管。 该晶体管包括源极或漏极第一区域以及通过沟道连接的漏极或源极第二区域。 栅极结构位于所述通道的顶部并且用于控制通道。 栅极结构形成在其侧壁具有朝向衬底的宽度尺寸收敛（窄））的形状的沟槽中。 电容器也形成为具有在电极之间的第一电极，第二电极和电介质层。 该电容器也形成在沟槽中。 电极线连接到电容器的第一电极。 电容器的第二电极形成在与晶体管的漏极或源极第二区域的至少一部分共同共享的层中。 位线位于门结构下方。 集成电路例如可以是DRAM存储单元。

    TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE 有权
    提供半导体存储器件的技术

    公开(公告)号：US20100259964A1

    公开(公告)日：2010-10-14

    申请号：US12751245

    申请日：2010-03-31

    申请人： Michael A. Van Buskirk ,  Christian Caillat ,  Viktor I. Koldiaev ,  Jungtae Kwon ,  Pierre C. Fazan

    发明人： Michael A. Van Buskirk ,  Christian Caillat ,  Viktor I. Koldiaev ,  Jungtae Kwon ,  Pierre C. Fazan

    IPC分类号： G11C5/06

    CPC分类号： H01L29/1095 ,  H01L21/76264 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10891 ,  H01L29/7841

    摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation of the array and a second barrier wall extending in the second orientation of the array and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.

    摘要翻译： 公开了一种用于提供半导体存储器件的技术。 在一个特定示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储器单元的半导体存储器件。 每个存储单元可以包括连接到沿第一取向延伸的源极线的第一区域。 每个存储单元还可以包括连接到延伸第二取向的位线的第二区域。 每个存储器单元还可以包括与字线间隔开并且电容耦合到字线的主体区域，其中所述主体区域电浮动并且设置在所述第一区域和所述第二区域之间。 半导体器件还可以包括沿阵列的第一取向延伸的第一阻挡壁和在阵列的第二取向延伸并且与第一阻挡壁相交的第二阻挡壁，以形成沟槽区域，该沟槽区域被配置为容纳多个 的记忆细胞。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08748959B2

    公开(公告)日：2014-06-10

    申请号：US12751245

    申请日：2010-03-31

    申请人： Michael A. Van Buskirk ,  Christian Caillat ,  Viktor I Koldiaev ,  Jungtae Kwon ,  Pierre C. Fazan

    发明人： Michael A. Van Buskirk ,  Christian Caillat ,  Viktor I Koldiaev ,  Jungtae Kwon ,  Pierre C. Fazan

    IPC分类号： H01L27/108 ,  H01L21/762

    CPC分类号： H01L29/1095 ,  H01L21/76264 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10891 ,  H01L29/7841

    摘要： A semiconductor memory device is disclosed. In one particular exemplary embodiment, the semiconductor memory device includes a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region connected to a source line extending in a first orientation. Each memory cell may also include a second region connected to a bit line extending a second orientation. Each memory cell may further include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The semiconductor device may also include a first barrier wall extending in the first orientation and a second barrier wall extending in the second orientation and intersecting with the first barrier wall to form a trench region configured to accommodate each of the plurality of memory cells.

    摘要翻译： 公开了一种半导体存储器件。 在一个特定的示例性实施例中，半导体存储器件包括以行和列的阵列排列的多个存储器单元。 每个存储单元可以包括连接到沿第一取向延伸的源极线的第一区域。 每个存储单元还可以包括连接到延伸第二取向的位线的第二区域。 每个存储器单元还可以包括与字线间隔开并且电容耦合到字线的主体区域，其中所述主体区域电浮动并且设置在所述第一区域和所述第二区域之间。 半导体器件还可以包括在第一取向上延伸的第一阻挡壁和在第二取向上延伸并与第一阻挡壁相交的第二阻挡壁，以形成配置成容纳多个存储单元中的每一个的沟槽区。