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公开(公告)号：US07835453B2
公开(公告)日：2010-11-16
申请号：US12350120
申请日：2009-01-07
IPC分类号： H04B3/00
CPC分类号： H04L25/0274 , H03F3/45197 , H03F2200/543 , H03F2203/45488
摘要： A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated.
摘要翻译： 驱动器电路被配置为具有耦合到第一数据信号的一个输入和耦合到第二数据信号的第二输入的频率补偿差分放大器。 差分放大器的每个级都用电流源偏置。 驱动器电路产生耦合到第一传输线的输入的第一输出信号和耦合到第二传输线的输入的第二输出信号。 第一和第二输出信号被产生为由补偿增益放大的第一和第二数据信号之间的差。 相对于高频分量衰减输入信号的低频分量的补偿网络耦合在偏置差分放大器的电流源之间。 第一和第二传输线的输出耦合到差分接收机的输入端，该差分接收机可以被频率补偿也可以不被频率补偿。
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公开(公告)号：US20090113107A1
公开(公告)日：2009-04-30
申请号：US12350120
申请日：2009-01-07
CPC分类号： H04L25/0274 , H03F3/45197 , H03F2200/543 , H03F2203/45488
摘要： A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated.
摘要翻译： 驱动器电路被配置为具有耦合到第一数据信号的一个输入和耦合到第二数据信号的第二输入的频率补偿差分放大器。 差分放大器的每个级都用电流源偏置。 驱动器电路产生耦合到第一传输线的输入的第一输出信号和耦合到第二传输线的输入的第二输出信号。 第一和第二输出信号被产生为由补偿增益放大的第一和第二数据信号之间的差。 相对于高频分量衰减输入信号的低频分量的补偿网络耦合在偏置差分放大器的电流源之间。 第一和第二传输线的输出耦合到差分接收机的输入端，该差分接收机可以被频率补偿也可以不被频率补偿。
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13.发明申请Method for Detecting Noise Events in Systems with Time Variable Operating Points 失效用于检测具有时间可变工作点的系统中的噪声事件的方法公开(公告)号：US20090048794A1
公开(公告)日：2009-02-19
申请号：US12262021
申请日：2008-10-30
申请人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
发明人： Daniel Douriet , Anand Haridass , Andreas Huber , Colm B. O'Reilly , Bao G. Truong , Roger D. Weekly
IPC分类号： G06F19/00
CPC分类号： G06F1/305
摘要： A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.
摘要翻译： 提供了一种用于检测具有时间可变操作点的系统中的噪声事件的电路。 将经过时间平均的第一电压与第二电压进行比较。 生成信号以指示处理器内的电路以启动动作以使电压进一步下降。
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14.发明授权公开(公告)号：US07477068B2
公开(公告)日：2009-01-13
申请号：US12058689
申请日：2008-03-29
IPC分类号： H03K17/16
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。
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15.发明授权公开(公告)号：US07382151B1
公开(公告)日：2008-06-03
申请号：US11611200
申请日：2006-12-15
IPC分类号： H03K17/16
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。
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公开(公告)号：US07242249B2
公开(公告)日：2007-07-10
申请号：US11055806
申请日：2005-02-11
IPC分类号： H03F3/45 , H03K19/094
CPC分类号： G11C7/1078 , G11C7/02 , G11C7/1084
摘要： A receiver circuit is configured as a frequency compensated differential amplifier having one input coupled to the output of a transmission line to receive a transmitted signal and the second input coupled to a reference voltage. The differential amplifier has a high frequency gain equivalent to the gain of an uncompensated differential stage for the transmitted signal. The compensated differential amplifier has an attenuated low frequency gain for signal frequencies substantially lower than the high frequency and a transitional gain for frequencies between the low and high frequencies. A compensated stage provides the portion of the signal with a compensated response and an uncompensated stage provides the portion of the amplified signal that is uncompensated. Bias control signals determine how much of the output signal is from the compensated and uncompensated stages as a means for customizing response from transmission lines with varying losses.
摘要翻译： 接收器电路被配置为频率补偿差分放大器，其具有耦合到传输线的输出的一个输入以接收传输的信号，而第二输入耦合到参考电压。 差分放大器具有等于发射信号的未补偿差分级的增益的高频增益。 补偿的差分放大器对于低于高频的信号频率具有衰减的低频增益，对于低频和高频之间的频率具有过渡增益。 补偿级为信号的一部分提供补偿响应，并且未补偿级提供未被补偿的放大信号的部分。 偏置控制信号确定来自补偿和无补偿级的输出信号的大小是用于定制来自具有不同损耗的传输线的响应的手段。
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17.发明授权Ceramic package in which far end noise is reduced using capacitive cancellation by offset wiring 有权陶瓷封装，其中通过偏移布线使用电容消除来减少远端噪声公开(公告)号：US07904849B2
公开(公告)日：2011-03-08
申请号：US11951705
申请日：2007-12-06
申请人： Anand Haridass , Andreas Huber , Bao G. Truong , Roger D. Weekly
发明人： Anand Haridass , Andreas Huber , Bao G. Truong , Roger D. Weekly
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , Y10T29/49155 , Y10T29/49163 , H01L2924/00
摘要： A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.
摘要翻译： 提供了一种用于减少由于来自多层陶瓷封装的其它信号面中的信号线的感应影响而在信号线中遭受的垂直串扰干扰的机制。 利用该装置和方法，多层陶瓷封装中的一个或多个通孔可以从结构中移除以提供信号线的偏移通过的区域。 由于信号线的这些偏移存在于彼此之上或之下的并行平面中，在这些信号线偏移之间没有直接存在接地线，所以在信号线中引入电容性串扰。 该电容串扰与信号线已经经历的电感串扰的极性相反。 结果，电容串扰倾向于消除或减少电感串扰，从而减少信号线中的远端噪声。
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18.发明授权Apparatus and method for far end noise reduction using capacitive cancellation by offset wiring 有权通过偏移布线使用电容消除进行远端降噪的装置和方法公开(公告)号：US07430800B2
公开(公告)日：2008-10-07
申请号：US11146441
申请日：2005-06-06
申请人： Anand Haridass , Andreas Huber , Bao G. Truong , Roger D. Weekly
发明人： Anand Haridass , Andreas Huber , Bao G. Truong , Roger D. Weekly
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , Y10T29/49155 , Y10T29/49163 , H01L2924/00
摘要： A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.
摘要翻译： 提供了一种用于减少由于来自多层陶瓷封装的其它信号面中的信号线的感应影响而在信号线中遭受的垂直串扰干扰的机制。 利用该装置和方法，多层陶瓷封装中的一个或多个通孔可以从结构中移除以提供信号线的偏移通过的区域。 由于信号线的这些偏移存在于彼此之上或之下的并行平面中，在这些信号线偏移之间没有直接存在接地线，所以在信号线中引入电容性串扰。 该电容串扰与信号线已经经历的电感串扰的极性相反。 结果，电容串扰倾向于消除或减少电感串扰，从而减少信号线中的远端噪声。
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19.发明申请公开(公告)号：US20080143375A1
公开(公告)日：2008-06-19
申请号：US11611200
申请日：2006-12-15
IPC分类号： H03K19/00 , H03K19/003
CPC分类号： H04L25/45
摘要： A first clock signal of frequency F is used to couple data to an off-chip driver (OCD) using a master/slave flip flop (FF), wherein the master latch is clocked with the first clock signal and the slave latch is clocked with the complement of the first clock signal. A second clock signal of frequency F/2 is generated from the first clock signal. The second clock signal is shifted a time equal to substantially one-half the cycle of the first clock signal. In one embodiment, the second clock is shifted using a delay line circuit. In another embodiment, the second clock is shifted using a master/slave FF, wherein the master latch is clocked with the complement of the first clock signal and the slave latch is clocked with the first clock signal. The logic state transitions of the data between edges of the propagating clock thereby reducing coupling to the clock transitions and thus reducing edge jitter.
摘要翻译： 使用频率F的第一时钟信号用于使用主/从触发器（FF）将数据耦合到片外驱动器（OCD），其中主锁存器由第一时钟信号计时，从锁存器以 第一个时钟信号的补码。 从第一时钟信号产生频率为F / 2的第二时钟信号。 第二时钟信号被移位等于第一时钟信号的周期的大致一半的时间。 在一个实施例中，使用延迟线电路来移位第二时钟。 在另一个实施例中，使用主/从FF来移位第二时钟，其中主锁存器用第一时钟信号的补码进行计时，从锁存器用第一时钟信号计时。 传播时钟的边缘之间的数据的逻辑状态转换，从而减少与时钟转换的耦合，从而减少边缘抖动。
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公开(公告)号：US07233170B2
公开(公告)日：2007-06-19
申请号：US11211955
申请日：2005-08-25
申请人： Wiren Dale Becker , Anand Haridass , Bao G. Truong
发明人： Wiren Dale Becker , Anand Haridass , Bao G. Truong
IPC分类号： H03K19/00
CPC分类号： H03K5/00 , H03K5/135 , H04L25/0276
摘要： Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a common clock signal as determined by a select signal from a skew controller. The differential signals are received in a differential receiver and a phase detector. The output of the phase detector in each differential channel is routed through an N×1 MUX. The N×1 MUX is controlled by the skew controller. The output of the N×1 MUX is fed back as a phase error feedback signal to the skew controller. Each differential data channel is sequentially selected and the programmable delays are adjusted until the phase error feedback signal from the selected phase detector reaches a predetermined minimum allowable value. Periodic adjustment may be implemented for calibration.
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