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11.发明申请CONFIGURABLE PRE-EMPHASIS DRIVER WITH SELECTIVE CONSTANT AND ADJUSTABLE OUTPUT IMPEDANCE MODES 失效具有选择性恒定和可调输出阻抗模式的可配置的前置驱动器公开(公告)号：US20100177830A1
公开(公告)日：2010-07-15
申请号：US12354007
申请日：2009-01-15
IPC分类号： H04B3/00
CPC分类号： H04B3/145
摘要： Embodiments of the invention are directed to a single driver that can be used to transmit data with configurable levels of pre-emphasis, and can have either a constant or adjustable driver output impendence, selectively. One embodiment, directed to a driver apparatus, is associated with a digital communication channel for transmitting data signals, wherein at least one of the signals includes a higher frequency component. The apparatus comprises a first sub-driver that has a constant output impedance, and is selectively configurable to implement two or more different levels of pre-emphasis. The apparatus further comprises one or more second sub-drivers. A set of connector elements are provided for connecting the first sub-driver and each of the second sub-drivers in parallel relationship with one another, so that the first sub-driver and each of the second sub-drivers all have inputs that respectively receive a specified driver apparatus input signal, and all have outputs that are connected together to selectively provide a specified driver apparatus output impedance. The apparatus further includes a device that is connected to selectively disable and enable each of the second sub-drivers.
摘要翻译： 本发明的实施例涉及可用于传输具有可配置水平的预加重的数据的单个驱动器，并且可以选择性地具有恒定的或可调节的驱动器输出阻抗。 针对驱动器装置的一个实施例与用于传输数据信号的数字通信信道相关联，其中信号中的至少一个包括较高频率分量。 该装置包括具有恒定输出阻抗的第一子驱动器，并且可选择性地配置为实现两个或多个不同级别的预加重。 该装置还包括一个或多个第二子驱动器。 提供了一组连接器元件，用于将第一子驱动器和每个第二子驱动器彼此并联连接，使得第一子驱动器和每个第二子驱动器都具有分别接收的输入 指定的驱动器装置输入信号，并且都具有连接在一起的输出，以选择性地提供指定的驱动器装置输出阻抗。 该装置还包括被连接以选择性地禁用并启用每个第二子驱动器的装置。
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公开(公告)号：US20100005349A1
公开(公告)日：2010-01-07
申请号：US12165848
申请日：2008-07-01
IPC分类号： G06F11/00
CPC分类号： G06F11/2007 , G06F11/0724 , G06F11/076 , H04L1/20
摘要： A processing device, processing system, method, and design structure for an enhanced microprocessor interconnect with bit shadowing are provided. The processing device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The processing device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译： 提供了一种用于具有位阴影的增强型微处理器互连的处理装置，处理系统，方法和设计结构。 处理装置包括阴影选择逻辑以选择驱动器位位置作为阴影驱动器值，以及线驱动器，用于在总线的单独链路段上传送所选择的驱动器位位置和阴影驱动器值的数据。 处理装置还包括阴影比较逻辑，以将所选接收值与来自总线的阴影接收值进行比较，并根据比较不匹配识别错误比较，并且阴影计数器计数误差相对于总线误差的速率 率一段时间。 响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。
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公开(公告)号：US20090201064A1
公开(公告)日：2009-08-13
申请号：US12028973
申请日：2008-02-11
IPC分类号： H03K3/00
CPC分类号： H03K5/15026 , H03B27/00 , H03H7/21 , H03H11/22 , H03K5/13 , H03K2005/00052 , H03K2005/00065 , H03K2005/00293
摘要： A phase interpolator system is disclosed that may include a clock to provide a clock signal, and a control section in communication with the clock to regulate the strength of the clock signal. The system may also include a generator circuit to produce an alternate clock signal based upon the strength of the clock signal received from the control section.
摘要翻译： 公开了可以包括提供时钟信号的时钟以及与时钟通信以调节时钟信号的强度的控制部分的相位内插器系统。 该系统还可以包括发电机电路，以根据从控制部分接收的时钟信号的强度来产生替代时钟信号。
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公开(公告)号：US07521968B2
公开(公告)日：2009-04-21
申请号：US11055852
申请日：2005-02-11
IPC分类号： H03K19/0175
CPC分类号： H03K17/164
摘要： The slew rate of signals output from an integrated circuit is selectively controlled to optimize the quality of the output data signal depending upon whether the communication channels require a faster or slower slew rate. Faster slew rates may be utilized when the communication channels are prone to attenuation, while slower slew rates may be implemented in the communication channels when crosstalk is more of a concern.
摘要翻译： 选择性地控制从集成电路输出的信号的转换速率，以根据通信信道是否需要更快或更慢的转换速率来优化输出数据信号的质量。 当通信信道易于衰减时，可以利用更快的转换速率，而当串扰更受关注时，可以在通信信道中实现较慢的转换速率。
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公开(公告)号：US20080183957A1
公开(公告)日：2008-07-31
申请号：US12060992
申请日：2008-04-02
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.
摘要翻译： 双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将 打包内存界面。 该卡片包括至少276个配置在其上的针脚。
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公开(公告)号：US20080005496A1
公开(公告)日：2008-01-03
申请号：US11383989
申请日：2006-05-18
IPC分类号： G06F13/00
CPC分类号： G06F13/1684 , G06F13/1673 , G06F13/1678 , Y02D10/14
摘要： Memory systems are disclosed that include a memory controller and an outbound link with the memory controller connected to the outbound link. The outbound link typically includes a number of conductive pathways that conduct memory signals from the memory controller to memory buffer devices in a first memory layer; and at least two memory buffer devices in a first memory layer. Each memory buffer device in the first memory layer typically is connected to the outbound link to receive memory signals from the memory controller.
摘要翻译： 公开了包括存储器控制器和与存储器控制器连接到出站链路的出站链路的存储器系统。 出站链路通常包括将存储器信号从存储器控制器传送到第一存储器层中的存储器缓冲器件的多个导电路径; 以及在第一存储器层中的至少两个存储缓冲器件。 第一存储器层中的每个存储器缓冲器件通常连接到出站链路以从存储器控制器接收存储器信号。
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公开(公告)号：US07239213B2
公开(公告)日：2007-07-03
申请号：US11209549
申请日：2005-08-23
IPC分类号： H01P1/00
CPC分类号： H04L25/0272 , H04B3/32
摘要： Signaling between two or more ICs use a signaling scheme wherein a reference signal is generated at the driver side and the receiver side. The driver side reference signal is coupled to the receiver side reference signal with a transmission line channel forming a reference channel. Data signal channels are paired with a reference channel between each two adjacent data channels. Adjacent pairs of data signal channels are each separated with an empty wiring channel. The paired data signals are received in one input of a differential receiver. The reference signal of the reference channel between the two paired data channels is coupled to the other input of the two differential receivers. Coupling from the paired data channels to the reference channel appears a common mode noise and is rejected by the differential receivers. The number of channels is reduced from a full differential signaling scheme.
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18.发明授权Method and apparatus for minimizing threshold variation from body charge in silicon-on-insulator circuitry 有权用于最小化绝缘体上硅电路中体电荷的阈值变化的方法和装置公开(公告)号：US07129859B2
公开(公告)日：2006-10-31
申请号：US10896504
申请日：2004-07-22
申请人： Daniel M. Dreps , Robert J. Reese , Hector Saenz
发明人： Daniel M. Dreps , Robert J. Reese , Hector Saenz
IPC分类号： H03M7/00
CPC分类号： H04L25/03866 , H04L7/0008
摘要： Circuitry used to de-skew data channels coupling parallel data signals over a communication link employs SOI circuitry that is subject to generating pulse distortion due to the history effect modifying threshold voltages. To substantially eliminate the pulse distortion, data signals are XOR with a repeating scramble data pattern that generates scrambled data with a minimum average ratio of logic ones to logic zeros logic zeros to logic ones. The scrambled data is sent over the communication link and de-skewed in the SOI circuitry with little or no pulse distortion. The scramble data pattern is again generated at the receiver side of the communication link after a delay time to synchronize the logic states of the scramble data pattern that generated the scrambled data with the scrambled data at the receiver side. The delayed scrambled data pattern is again XOR'ed with the scrambled data to recover the data signal.
摘要翻译： 用于对通过通信链路耦合并行数据信号的数据信道进行去偏移的电路采用由于历史效应修改阈值电压而产生脉冲失真的SOI电路。 为了基本上消除脉冲失真，数据信号是具有重复加扰数据模式的XOR，其产生具有逻辑1到逻辑0到逻辑1的最小平均比的逻辑1的加扰数据。 加扰的数据通过通信链路发送，并且在SOI电路中具有很少或没有脉冲失真的去偏移。 在延迟时间之后，在通信链路的接收机侧再次产生加扰数据模式，以将产生加扰数据的加扰数据模式的逻辑状态与接收机侧的加扰数据进行同步。 延迟加扰的数据模式与加扰的数据再次被异或以恢复数据信号。
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公开(公告)号：US5027183A
公开(公告)日：1991-06-25
申请号：US513310
申请日：1990-04-20
申请人： Daniel M. Dreps
发明人： Daniel M. Dreps
IPC分类号： H01L21/76 , H01L21/761 , H01L27/082
CPC分类号： H01L21/761 , H01L27/0823
摘要： Individual stages of a multistage electronic receiver include a pair of conductive isolation regions around each stage to isolate each stage from the other stages and thereby prevent feedback and external noise problems. Each pair of isolation regions includes a P+ ring and an N+ ring adjacent to each other to shunt hole carriers and electron carriers, respectively. Removal of the carriers does not have to wait for recombination of the carriers. The region which has the same conductivity type as the substrate extends entirely through an epitaxial or diffused layer to the substrate to collect hole carriers in the substrate.
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公开(公告)号：US20120260016A1
公开(公告)日：2012-10-11
申请号：US13080799
申请日：2011-04-06
IPC分类号： G06F13/14
CPC分类号： G06F13/385 , G06F1/10 , G06F13/4072 , G11C7/1006 , G11C7/1066 , G11C7/1093
摘要： A multi-use physical (PHY) architecture that includes a PHY connection that includes one or more bit lines and that is communicatively coupled to a first processor. The PHY connection is configurable to carry signals between the first processor and a second processor, or between the first processor and a memory. The one or more bit lines are configured to carry signals bi-directionally at a first voltage when the PHY connection is configured to carry signals between the first processor and the memory. The one or more bit lines are configured to carry signals uni-directionally at a second voltage when the PHY connection is configured to carry signals between the first processor and the second processor. The second voltage is different than the first voltage.
摘要翻译： 一种多用途物理（PHY）架构，其包括包括一个或多个位线并且通信地耦合到第一处理器的PHY连接。 PHY连接可配置为在第一处理器和第二处理器之间或第一处理器和存储器之间传送信号。 一个或多个位线被配置为当PHY连接被配置为在第一处理器和存储器之间传送信号时以双向方式携带信号处于第一电压。 当PHY连接被配置为在第一处理器和第二处理器之间传送信号时，一个或多个位线被配置为以第二电压单向地传送信号。 第二电压不同于第一电压。
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