公开(公告)号：US08493771B2

公开(公告)日：2013-07-23

申请号：US13570871

申请日：2012-08-09

申请人： Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Roy Lambertson ,  Rene Meyer

发明人： Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Roy Lambertson ,  Rene Meyer

IPC分类号： G11C11/21

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

摘要： An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.

摘要翻译： 由与电绝缘层接触的介电材料制成的离子阻挡层可操作以防止在对非易失性存储单元的数据操作期间传输到电绝缘层中的移动离子通过离子阻挡层并进入相邻层。 与电绝缘层接触的导电氧化物层是可移动离子的源。 编程数据操作用于将一部分移动离子传输到电绝缘层中，并且擦除数据操作可操作以将移动离子传输回到导电氧化物层中。 当该部分位于电绝缘层中时，存储单元将数据存储为编程电导率分布，并且当大部分移动离子位于导电氧化物层中时，存储单元将数据存储为擦除的电导率分布。

公开(公告)号：US08274817B2

公开(公告)日：2012-09-25

申请号：US13281335

申请日：2011-10-25

申请人： Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Roy Lambertson ,  Rene Meyer

发明人： Lawrence Schloss ,  Julie Casperson Brewer ,  Wayne Kinney ,  Roy Lambertson ,  Rene Meyer

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

摘要： An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.

摘要翻译： 由与电绝缘层接触的介电材料制成的离子阻挡层可操作以防止在对非易失性存储单元的数据操作期间传输到电绝缘层中的移动离子通过离子阻挡层并进入相邻层。 与电绝缘层接触的导电氧化物层是可移动离子的源。 编程数据操作用于将一部分移动离子传输到电绝缘层中，并且擦除数据操作可操作以将移动离子传输回到导电氧化物层中。 当该部分位于电绝缘层中时，存储单元将数据存储为编程电导率分布，并且当大部分移动离子位于导电氧化物层中时，存储单元将数据存储为擦除的电导率分布。

公开(公告)号：US20120300535A1

公开(公告)日：2012-11-29

申请号：US13570871

申请日：2012-08-09

申请人： Lawrence Schloss ,  Rene Meyer ,  Wayne Kinney ,  Roy Lambertson ,  Julie Casperson Brewer

发明人： Lawrence Schloss ,  Rene Meyer ,  Wayne Kinney ,  Roy Lambertson ,  Julie Casperson Brewer

IPC分类号： H01L45/00 ,  G11C11/21

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

摘要： An ion barrier layer made from a dielectric material in contact with an electronically insulating layer is operative to prevent mobile ions transported into the electronically insulating layer from passing through the ion barrier layer and into adjacent layers during data operations on a non-volatile memory cell. A conductive oxide layer in contact with the electronically insulating layer is the source of the mobile ions. A programming data operation is operative to transport a portion of the mobile ions into the electronically insulating layer and an erase data operation is operative to transport the mobile ions back into the conductive oxide layer. When the portion is positioned in the electronically insulating layer the memory cell stores data as a programmed conductivity profile and when a substantial majority of the mobile ions are positioned in the conductive oxide layer the memory cell stores data as an erased conductivity profile.

摘要翻译： 由与电绝缘层接触的介电材料制成的离子阻挡层可操作以防止在对非易失性存储单元的数据操作期间传输到电绝缘层中的移动离子通过离子阻挡层并进入相邻层。 与电绝缘层接触的导电氧化物层是可移动离子的源。 编程数据操作用于将一部分移动离子传输到电绝缘层中，并且擦除数据操作可操作以将移动离子传输回到导电氧化物层中。 当该部分位于电绝缘层中时，存储单元将数据存储为编程电导率分布，并且当大部分移动离子位于导电氧化物层中时，存储单元将数据存储为擦除的电导率分布。

公开(公告)号：US20100159641A1

公开(公告)日：2010-06-24

申请号：US12653851

申请日：2009-12-18

申请人： Darrell Rinerson ,  Jonathan Bornstein ,  David Hansen ,  Robin Cheung ,  Steven W. Longcor ,  Rene Meyer ,  Lawrence Schloss

发明人： Darrell Rinerson ,  Jonathan Bornstein ,  David Hansen ,  Robin Cheung ,  Steven W. Longcor ,  Rene Meyer ,  Lawrence Schloss

IPC分类号： H01L21/34

CPC分类号： F01D17/26 ,  F04D29/563 ,  H01L21/02565 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1666

摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

摘要翻译： 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOX，LaSrCoOX，LaNiOX等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触，并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。

公开(公告)号：US08003511B2

公开(公告)日：2011-08-23

申请号：US12653851

申请日：2009-12-18

申请人： Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Steven W. Longcor ,  Rene Meyer ,  Lawrence Schloss

发明人： Darrell Rinerson ,  Jonathan Bornstein ,  Robin Cheung ,  David Hansen ,  Steven W. Longcor ,  Rene Meyer ,  Lawrence Schloss

IPC分类号： H01L21/44

CPC分类号： F01D17/26 ,  F04D29/563 ,  H01L21/02565 ,  H01L27/0688 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1666

摘要： Memory cell formation using ion implant isolated conductive metal oxide is disclosed, including forming a bottom electrode below unetched conductive metal oxide layer(s), forming the unetched conductive metal oxide layer(s) including depositing at least one layer of a conductive metal oxide (CMO) material (e.g., PrCaMnOX, LaSrCoOX, LaNiOX, etc.) over the bottom electrode. At least one portion of the layer of CMO is configured to act as a memory element without etching, and performing ion implantation on portions of the layer(s) of CMO to create insulating metal oxide (IMO) regions in the layer(s) of CMO. The IMO regions are positioned adjacent to electrically conductive CMO regions in the unetched layer(s) of CMO and the electrically conductive CMO regions are disposed above and in contact with the bottom electrode and form memory elements operative to store non-volatile data as a plurality of conductivity profiles (e.g., resistive states indicative of stored data).

摘要翻译： 公开了使用离子注入隔离的导电金属氧化物的存储单元形成，包括在未蚀刻的导电金属氧化物层之下形成底部电极，形成未蚀刻的导电金属氧化物层，包括沉积至少一层导电金属氧化物（ CMO）材料（例如，PrCaMnOX，LaSrCoOX，LaNiOX等）。 CMO层的至少一部分被配置为用作存储元件而不进行蚀刻，并且在CMO的层的部分上执行离子注入以在层的一个或多个层中形成绝缘金属氧化物（IMO）区域 CMO。 IMO区域邻近CMO的未蚀刻层中的导电CMO区域定位，并且导电CMO区域设置在底部电极的上方并与底部电极接触，并且形成用于将非易失性数据存储为多个的存储元件 （例如，表示存储数据的电阻状态）。

公开(公告)号：US08254196B2

公开(公告)日：2012-08-28

申请号：US13246654

申请日：2011-09-27

申请人： Roy Lambertson ,  Lawrence Schloss

发明人： Roy Lambertson ,  Lawrence Schloss

IPC分类号： G11C7/00

CPC分类号： H01L45/146 ,  G11C11/36 ,  G11C13/003 ,  G11C29/006 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021

摘要： A two-terminal memory cell including a Schottky metal-semiconductor contact as a selection device (SD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The SD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The SD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied.

摘要翻译： 包括肖特基金属 - 半导体触点作为选择装置（SD）的双端存储单元允许选择两端交叉点存储阵列工作电压，以消除当其它类型的非 - 使用欧姆器件。 SD结构可以包括“金属/氧化物半导体/金属”或“金属/轻掺杂单层多晶硅”。存储单元可以包括两端存储元件，其包括至少一个导电氧化物层（例如， 导电金属氧化物-CMO，例如钙钛矿或导电二元氧化物）和与CMO接触的电子绝缘层（例如，氧化钇稳定的氧化锆-YSZ）。 SD可以被包括在存储单元中并与存储元件串联构造。 存储器单元可以位于一对导电阵列线（例如，位线和字线）之间的两端交叉点阵列中，用于数据操作的电压被施加在该两端交叉点阵列上。

公开(公告)号：US20100157710A1

公开(公告)日：2010-06-24

申请号：US12584262

申请日：2009-09-02

申请人： Roy Lambertson ,  Lawrence Schloss

发明人： Roy Lambertson ,  Lawrence Schloss

IPC分类号： G11C7/00 ,  H01L29/04 ,  H01L29/12 ,  G11C11/36

CPC分类号： H01L45/146 ,  G11C11/36 ,  G11C13/003 ,  G11C29/006 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021

摘要： A two-terminal memory cell including a Schottky metal-semiconductor contact as a non-ohmic device (NOD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The NOD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The NOD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied.

摘要翻译： 包括肖特基金属 - 半导体接触作为非欧姆器件（NOD）的两端存储单元允许选择两端交叉点存储器阵列工作电压，以消除当其它类型的 使用非欧姆器件。 NOD结构可以包括“金属/氧化物半导体/金属”或“金属/轻掺杂的单层多晶硅”。存储单元可以包括两端存储元件，其包括至少一个导电氧化物层（例如， 导电金属氧化物-CMO，例如钙钛矿或导电二元氧化物）和与CMO接触的电子绝缘层（例如，氧化钇稳定的氧化锆-YSZ）。 NOD可以被包括在存储器单元中并与存储元件串联构成。 存储器单元可以位于一对导电阵列线（例如，位线和字线）之间的两端交叉点阵列中，用于数据操作的电压被施加在该两端交叉点阵列上。

公开(公告)号：US08027215B2

公开(公告)日：2011-09-27

申请号：US12584262

申请日：2009-09-02

申请人： Roy Lambertson ,  Lawrence Schloss

发明人： Roy Lambertson ,  Lawrence Schloss

IPC分类号： G11C7/00

CPC分类号： H01L45/146 ,  G11C11/36 ,  G11C13/003 ,  G11C29/006 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021

摘要： A two-terminal memory cell including a Schottky metal-semiconductor contact as a non-ohmic device (NOD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The NOD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The NOD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied.

摘要翻译： 包括肖特基金属 - 半导体接触作为非欧姆器件（NOD）的两端存储单元允许选择两端交叉点存储器阵列工作电压，以消除当其它类型的 使用非欧姆器件。 NOD结构可以包括“金属/氧化物半导体/金属”或“金属/轻掺杂的单层多晶硅”。存储单元可以包括两端存储元件，其包括至少一个导电氧化物层（例如， 导电金属氧化物-CMO，例如钙钛矿或导电二元氧化物）和与CMO接触的电子绝缘层（例如，氧化钇稳定的氧化锆-YSZ）。 NOD可以被包括在存储器单元中并与存储元件串联构成。 存储器单元可以位于一对导电阵列线（例如，位线和字线）之间的两端交叉点阵列中，用于数据操作的电压被施加在该两端交叉点阵列上。

公开(公告)号：US08565039B2

公开(公告)日：2013-10-22

申请号：US13555873

申请日：2012-07-23

申请人： Roy Lambertson ,  Lawrence Schloss

发明人： Roy Lambertson ,  Lawrence Schloss

IPC分类号： G11C7/00

CPC分类号： H01L45/146 ,  G11C11/36 ,  G11C13/003 ,  G11C29/006 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021

摘要： A two-terminal memory cell including a Schottky metal-semiconductor contact as a selection device (SD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The SD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The SD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied.

摘要翻译： 包括肖特基金属 - 半导体触点作为选择装置（SD）的双端存储单元允许选择两端交叉点存储阵列工作电压，以消除当其它类型的非 - 使用欧姆器件。 SD结构可以包括“金属/氧化物半导体/金属”或“金属/轻掺杂单层多晶硅”。 存储器单元可以包括包括至少一个导电氧化物层（例如，导电金属氧化物-CMO，例如钙钛矿或导电二元氧化物）的两端存储元件和电绝缘层（例如，氧化钇稳定的氧化锆 -YSZ）与CMO接触。 SD可以被包括在存储单元中并与存储元件串联构造。 存储器单元可以位于一对导电阵列线（例如，位线和字线）之间的两端交叉点阵列中，用于数据操作的电压被施加在该两端交叉点阵列上。

公开(公告)号：US20120286232A1

公开(公告)日：2012-11-15

申请号：US13555873

申请日：2012-07-23

申请人： Roy Lambertson ,  Lawrence Schloss

发明人： Roy Lambertson ,  Lawrence Schloss

IPC分类号： H01L47/00

CPC分类号： H01L45/146 ,  G11C11/36 ,  G11C13/003 ,  G11C29/006 ,  G11C2213/71 ,  G11C2213/76 ,  H01L27/101 ,  H01L27/1021

摘要： A two-terminal memory cell including a Schottky metal-semiconductor contact as a selection device (SD) allows selection of two-terminal cross-point memory array operating voltages that eliminate “half-select leakage current” problems present when other types of non-ohmic devices are used. The SD structure can comprise a “metal/oxide semiconductor/metal” or a “metal/lightly-doped single layer polycrystalline silicon.” The memory cell can include a two-terminal memory element including at least one conductive oxide layer (e.g., a conductive metal oxide—CMO, such as a perovskite or a conductive binary oxide) and an electronically insulating layer (e.g., yttria-stabilized zirconia—YSZ) in contact with the CMO. The SD can be included in the memory cell and configured electrically in series with the memory element. The memory cell can be positioned in a two-terminal cross-point array between a pair of conductive array lines (e.g., a bit line and a word line) across which voltages for data operations are applied.

摘要翻译： 包括作为选择装置（SD）的肖特基金属 - 半导体触点的双端存储单元允许选择两端交叉点存储器阵列工作电压，以消除其它类型的非欧姆器件所存在的半选择漏电流问题 被使用。 SD结构可以包括金属/氧化物半导体/金属或金属/轻掺杂的单层多晶硅。 存储器单元可以包括包括至少一个导电氧化物层（例如，导电金属氧化物-CMO，例如钙钛矿或导电二元氧化物）的两端存储元件和电绝缘层（例如，氧化钇稳定的氧化锆 -YSZ）与CMO接触。 SD可以被包括在存储单元中并与存储元件串联构造。 存储器单元可以位于一对导电阵列线（例如，位线和字线）之间的两端交叉点阵列中，用于数据操作的电压被施加在该两端交叉点阵列上。