公开(公告)号：US5142633A

公开(公告)日：1992-08-25

申请号：US306846

申请日：1989-02-03

申请人： John E. Murray ,  David B. Fite ,  Mark A. Firstenberg

发明人： John E. Murray ,  David B. Fite ,  Mark A. Firstenberg

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/30054 ,  G06F9/30149 ,  G06F9/30163 ,  G06F9/30167 ,  G06F9/30178 ,  G06F9/34 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3824

摘要： An instruction decoder generates implied specifiers for certain predefined instructions, and an operand processing unit preprocess most of the implied specifiers in the same fashion as express operand specifiers. For instructions having an implied autoincrement or autodecrement of the stack pointer, an implied read or write access type is assigned to the instruction and the decode logic is configured accordingly. When an opcode is decoded and is found to have an implied write specifier, a destination operand is created for autodecrementing the stack pointer. If an opcode is decoded and found to have an implied read specifier, a source operand is created for autoincrementing the stack pointer. A register or short literal specifier can be decoded simultaneously with the generation of the implied operand. Therefore some common instructions such as "PUSH Rx" can be decoded in a single cycle. The preprocessing of implied specifiers in addition permits more complex instructions such as "BSR DEST" to be executed in a single cycle. Conflicts created by the implied specifiers are handled in the same manner as conflicts for express specifiers. Moreover, by using the same data paths for both the implied specifiers and the express specifiers, and by inserting queues between the instruction unit and the execution unit, performance gains are realized for instructions having implied specifiers as well as just express specifiers.

公开(公告)号：US5113515A

公开(公告)日：1992-05-12

申请号：US306831

申请日：1989-02-03

申请人： David B. Fite ,  Ricky C. Hetherington ,  Michael M. McKeon ,  Dwight P. Manley ,  John E. Murray

发明人： David B. Fite ,  Ricky C. Hetherington ,  Michael M. McKeon ,  Dwight P. Manley ,  John E. Murray

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30145 ,  G06F9/30149 ,  G06F9/3816

摘要： An instruction buffer of a high speed digital computer controls the flow of instruction stream to an instruction decoder. The buffer provides the decoder with nine bytes of sequential instruction stream. The instruction set used by the computer is of the variable length type, such that the decoder consumes a variable number of the instruction stream bytes, depending upon the type of instruction being decoded. As each instruction is consumed, a shifter removes the consumed bytes and repositions the remaining bytes into the lowest order positions. The byte positions left empty by the shifter are filled by instruction stream retrieved from one of a pair of prefetch buffers (IBEX, IBEX2) or from a virtual instruction cache. These prefetch buffers are arranged to hold the next two subsequent quadwords of instruction stream and provide the desired missing bytes. The IBEX prefetch buffer is filled from the instruction cache after being emptied, but prior to those particular bytes being requested to fill the instruction decoder. This two level prefetching allows the relatively slow process of cache access to be performed during noncritical time. The instruction decoder is not stalled, waiting for a cache refill, but can ordinarily obtain the desired bytes of instruction stream from the prefetch buffer.

公开(公告)号：US5167026A

公开(公告)日：1992-11-24

申请号：US306833

申请日：1989-02-03

申请人： John E. Murray ,  David B. Fite ,  Mark A. Firstenberg ,  Lawrence O. Herman ,  Ronald M. Salett

发明人： John E. Murray ,  David B. Fite ,  Mark A. Firstenberg ,  Lawrence O. Herman ,  Ronald M. Salett

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30167 ,  G06F9/30149 ,  G06F9/30163 ,  G06F9/30178 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3863

摘要： In a pipeline processor, simultaneous decoding of multiple specifiers in a variable-length instruction causes a peculiar problem of an intra-instruction read conflict that occurs whenever an instruction includes an autoincrement or an autodecrement specifier which references either directly or indirectly a register specified by a previously occurring specifier for the current instruction. To avoid stalls during the preprocessing of instructions by the instruction unit, register pointers rather than register data are usually passed to the excellent unit because register data is not always available at the time of instruction decoding. If an intra-instruction read conflict exists, however, the operand value specified by the conflicting register specifier is the initial value of the register being incremented or decremented, and this initial value will have been changed by the time that the execution unit executes the instruction. Preferably, the proper initial value is obtained prior to the incrementing or decrementing of the conflicting register by putting the instruction decoder into a special IRC mode in which only one specifier is decoded per cycle, and if a specifier being decoded is a register specifier, the content of the specified register is transmitted to the execution unit. Circuitry for detecting an intra-instruction read conflict is disclosed as well as an efficient method for handling interrupts, exceptions and flushes that may occur during the processing of an instruction having an intra-instruction read conflict.

公开(公告)号：US4548002A

公开(公告)日：1985-10-22

申请号：US427627

申请日：1982-09-29

申请人： John E. Murray

发明人： John E. Murray

IPC分类号： E04B7/00 ,  E04D13/155

CPC分类号： E04D13/155 ,  E04B7/00

摘要： A roof is disclosed for a mobile home or the like. The roof comprises an existing roof having peripheral blocks disposed along the entire peripheral edge of the existing roof. Insulative material overlies the existing roof and is encompassed by the peripheral blocks. Marginal flashing of impervious material overlies the peripheral blocks and includes a first and a second limb. An upstanding portion is disposed adjacent the distal end of the first limb. Supplementary roof sheets of impervious material overlie the insulative material, the upstanding portion and the first limb and a lag screw or the like secures the first limb between the supplementary roof sheets and the peripheral blocks.

摘要翻译： 公开了一种用于移动式家庭等的屋顶。 屋顶包括具有沿现有屋顶的整个周边边缘设置的外围块的现有屋顶。 绝缘材料覆盖在现有的屋顶上并被外围块包围。 不透水材料的边缘闪光覆盖在周边块上并且包括第一和第二肢体。 直立部分邻近第一肢体的远端设置。 不透水材料的补充屋顶片覆盖绝缘材料，直立部分和第一肢体以及拉力螺钉等将辅助屋顶片和周边块之间的第一肢固定。

公开(公告)号：US4380797A

公开(公告)日：1983-04-19

申请号：US165854

申请日：1980-07-07

申请人： Peter L. Desyllas ,  Barry G. Radley ,  Alasdair Rawsthorne ,  John R. Eaton ,  John E. Murray

发明人： Peter L. Desyllas ,  Barry G. Radley ,  Alasdair Rawsthorne ,  John R. Eaton ,  John E. Murray

IPC分类号： G06F12/10 ,  G06F17/30 ,  G06F13/00

CPC分类号： G06F17/30949 ,  G06F12/1027

摘要： A data processing system has a two-level storage system in which data items are copied from a main store into a smaller, faster slave store on demand. The mapping of the main store on to the slave store is a many-to-one mapping so that situations will occur where two required data items cannot both be present simultaneously in the slave store because they map on to the same location. The system has special logic which detects this situation and, upon detection, temporarily suspends the use of the slave store and instead uses a smaller first-in first-out area of storage.

摘要翻译： 数据处理系统具有两级存储系统，其中数据项从主存储被复制到更小更快的从存储器中。 主存储到从属存储的映射是多对一映射，因此在两个所需数据项不能同时存在于从属存储中的情况下将发生这种情况，因为它们映射到同一位置。 该系统具有检测这种情况的特殊逻辑，并且在检测到时，暂时停止使用从属存储，而是使用较小的先进先出存储区域。