公开(公告)号：US4380797A

公开(公告)日：1983-04-19

申请号：US165854

申请日：1980-07-07

申请人： Peter L. Desyllas ,  Barry G. Radley ,  Alasdair Rawsthorne ,  John R. Eaton ,  John E. Murray

发明人： Peter L. Desyllas ,  Barry G. Radley ,  Alasdair Rawsthorne ,  John R. Eaton ,  John E. Murray

IPC分类号： G06F12/10 ,  G06F17/30 ,  G06F13/00

CPC分类号： G06F17/30949 ,  G06F12/1027

摘要： A data processing system has a two-level storage system in which data items are copied from a main store into a smaller, faster slave store on demand. The mapping of the main store on to the slave store is a many-to-one mapping so that situations will occur where two required data items cannot both be present simultaneously in the slave store because they map on to the same location. The system has special logic which detects this situation and, upon detection, temporarily suspends the use of the slave store and instead uses a smaller first-in first-out area of storage.

摘要翻译： 数据处理系统具有两级存储系统，其中数据项从主存储被复制到更小更快的从存储器中。 主存储到从属存储的映射是多对一映射，因此在两个所需数据项不能同时存在于从属存储中的情况下将发生这种情况，因为它们映射到同一位置。 该系统具有检测这种情况的特殊逻辑，并且在检测到时，暂时停止使用从属存储，而是使用较小的先进先出存储区域。

公开(公告)号：US4187539A

公开(公告)日：1980-02-05

申请号：US819868

申请日：1977-07-28

申请人： John R. Eaton

发明人： John R. Eaton

IPC分类号： G06F9/22 ,  G06F9/28 ,  G06F9/38 ,  G06F9/20 ,  G06F9/06

CPC分类号： G06F9/3867

摘要： A pipelined data processing system having n processing stages, each of which is under the control of a central microprogram. Each microprogram instruction is decoded to produce n control signals, one for each processing stage. Microprogram start addresses are generated by combining information from the latest n program instructions received. Thus, each microprogram sequence implements a combination of phases of successive program instructions. A flag register is used to store relatively static control information, and effectively provides an extension of the microprogram instruction.

摘要翻译： 具有n个处理阶段的流水线数据处理系统，每个处理阶段处于中央微程序的控制之下。 每个微程序指令被解码以产生n个控制信号，每个处理阶段一个。 通过组合来自最新的n个程序指令的信息来生成微程序起始地址。 因此，每个微程序序列实现连续程序指令的相位组合。 标志寄存器用于存储相对静态的控制信息，有效地提供了微程序指令的扩展。

公开(公告)号：US5117490A

公开(公告)日：1992-05-26

申请号：US379057

申请日：1989-07-13

申请人： Colin M. Duxbury ,  John R. Eaton ,  Philip V. Rose

发明人： Colin M. Duxbury ,  John R. Eaton ,  Philip V. Rose

IPC分类号： G06F9/38

CPC分类号： G06F9/3865 ,  G06F9/30167 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3875 ,  G06F9/3889

摘要： Data processing apparatus comprises a series of pipeline units each of which consists of a number of pipeline stages. The units are interconnected by a number of parameter files, which provide a number of slots. Whenever an instruction is initiated in the pipeline, it is allocated a slot, and retains that slot until its execution is successfully completed. Two independent streams of instructions are scheduled through the pipeline, each being allocated a fixed number of the slots. In normal operation, one of the streams has priority over the other stream. An instruction is allowed to change the process state only when it successfully terminates at the end of the pipeline, thus ensuring consistency. An instruction can be started in a lower pipeline unit as soon as it is know that its required operand will be available in time from the data slave, thus allowing the operations of these two units to be overlapped.

公开(公告)号：US5347647A

公开(公告)日：1994-09-13

申请号：US737263

申请日：1991-07-29

申请人： George Allt ,  John R. Eaton

发明人： George Allt ,  John R. Eaton

IPC分类号： G06F11/34 ,  G06F1/00 ,  G06G7/48

CPC分类号： G06F11/3409 ,  G06F11/3419 ,  G06F11/3428 ,  G06F11/3457 ,  G06F11/3476

摘要： A method and apparatus as described for predicting the performance of a computer system. A benchmark program is run on an existing host computer, and is monitored to determine the actual sequence of instructions in the instruction set of the host. These are then converted into the corresponding sequence in the instruction set of the target. The performance of the target system in executing these instructions is then determined.

摘要翻译： 所描述的用于预测计算机系统的性能的方法和装置。 基准程序在现有主机上运行，​​并被监控以确定主机指令集中的指令的实际顺序。 然后将它们转换为目标的指令集中的相应序列。 然后确定执行这些指令时目标系统的性能。

公开(公告)号：US4736289A

公开(公告)日：1988-04-05

申请号：US822804

申请日：1986-01-27

申请人： John R. Eaton

发明人： John R. Eaton

IPC分类号： G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/30189 ,  G06F9/268 ,  G06F9/28 ,  G06F9/3861

摘要： A microprogrammed processor in which instructions have alternative fast and slow microprogram sequences. The fast sequences are designed for speed, and can detect exception conditions but do not resolve them. The slow sequences perform all the necessary tests to resolve these conditions. When a fast sequence detects an exception, that sequence is abandoned, and the corresponding slow sequence is run.

摘要翻译： 一种微程序处理器，其中指令具有备选的快速和慢速微程序序列。 快速序列是为速度设计的，可以检测异常情况，但不能解决它们。 慢序列执行所有必要的测试来解决这些情况。 当快速序列检测到异常时，该序列被放弃，并且运行相应的慢序列。

公开(公告)号：US5159675A

公开(公告)日：1992-10-27

申请号：US393418

申请日：1989-08-14

申请人： George Allt ,  John R. Eaton

发明人： George Allt ,  John R. Eaton

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3869

摘要： A data processor is provided with a mechanism for controlling its performance. The processor is allowed to run normally for R clock beats, and then further instruction starts are inhibited for W clock beats. The ratio W/R determines the level of performance of the processor.

公开(公告)号：US5040107A

公开(公告)日：1991-08-13

申请号：US374738

申请日：1989-07-03

申请人： Colin M. Duxbury ,  John R. Eaton ,  Philip V. Rose

发明人： Colin M. Duxbury ,  John R. Eaton ,  Philip V. Rose

IPC分类号： G06F9/38

CPC分类号： G06F9/3865 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3863 ,  G06F9/3867

摘要： In a pipelined data processor, when a dependency is detected between a first instruction and a second, subsequent instruction, the second instruction is abandoned. A look-ahead mode of operation is then initiated, in which instructions subsequent to the abandoned instruction are allowed to continue to be executed so as to pre-fetch operands, but are not allowed to be fully executed. The processor has two separate streams of instructions, each of which streams can be independently put into look-ahead mode. When one stream is in look-ahead mode, the other is given priority.

公开(公告)号：US4714991A

公开(公告)日：1987-12-22

申请号：US697484

申请日：1985-02-01

申请人： John R. Eaton

发明人： John R. Eaton

IPC分类号： G06F9/22 ,  G06F9/28

CPC分类号： G06F9/223

摘要： A data processing apparatus, which includes a microprogram control unit for producing control signals for the apparatus. Each microinstruction contains a number of control bits, and an address field. The address field addresses a control memory so as to read out a control word. Each control word specifies the way in which the control signals are mapped on to the control bits of the microinstruction. The output of the control memory controls switching logic which connects the control bits to the specified control signal lines. This variable mapping of the control signals allows the control signals to be packed into any available space in the microinstruction, thus reducing the required number of bits in the microinstruction without any significant loss of flexibility. Certain critical control signals however are derived from fixed positions in the microinstruction so as to avoid delays. These critical control signals are confirmed by validity signals from the control memory.

摘要翻译： 一种数据处理装置，包括用于产生装置的控制信号的微程序控制单元。 每个微指令包含多个控制位和一个地址字段。 地址字段寻址控制存储器，以读出控制字。 每个控制字指定控制信号映射到微指令的控制位的方式。 控制存储器的输出控制将控制位连接到指定的控制信号线的开关逻辑。 控制信号的这种可变映射允许将控制信号打包到微指令中的任何可用空间中，从而减少微指令中所需的位数，而不会有任何明显的灵活性损失。 然而，某些关键控制信号来自微指令中的固定位置，以避免延迟。 这些关键控制信号由来自控制存储器的有效信号确认。