公开(公告)号：US5771195A

公开(公告)日：1998-06-23

申请号：US758582

申请日：1996-11-27

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

CPC classification number: G11C29/24 ,  G11C29/785 ,  G11C29/80 ,  G11C29/808 ,  G11C29/84

Abstract: A memory access circuit is provided for isolating a matrix memory cell from and coupling a redundant memory cell to a data line when the matrix memory cell is defective. The memory access circuit includes a matrix switch that is coupled between the matrix memory cell and the data line. When the matrix memory cell is defective, a matrix-switch control circuit opens the matrix switch to isolate the defective memory cell from the data line. The memory access circuit also includes a redundant switch that is coupled between the redundant memory cell and the data line. When the defective matrix memory cell is addressed, a redundant-switch control circuit closes the redundant switch to couple the redundant memory cell to the data line in place of the defective memory cell.

Abstract translation: 提供存储器访问电路，用于当矩阵存储单元有缺陷时，将矩阵存储单元隔离并将冗余存储单元耦合到数据线。 存储器访问电路包括耦合在矩阵存储单元和数据线之间的矩阵开关。 当矩阵存储单元有缺陷时，矩阵切换控制电路打开矩阵开关，以将有缺陷的存储单元与数据线隔离。 存储器访问电路还包括耦合在冗余存储器单元和数据线之间的冗余开关。 当故障矩阵存储单元被寻址时，冗余开关控制电路关闭冗余开关以将冗余存储单元耦合到数据线来代替有缺陷的存储单元。

公开(公告)号：US5703512A

公开(公告)日：1997-12-30

申请号：US712960

申请日：1996-09-12

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G01R31/317 ,  G06F11/22 ,  H03K17/22

CPC classification number: G01R31/31701 ,  G06F11/22

Abstract: An integrated circuit includes test circuitry and test mode enable circuitry. During power-up, an over-voltage on a package pin of the integrated circuit can initiate a test mode. The test mode enable signal may be latched into its activity state by a signal provided on a second package pin. Thereafter, the first and second package pins may be used in the normal voltage range during the test operations.

Abstract translation: 集成电路包括测试电路和测试模式使能电路。 在上电期间，集成电路的封装引脚上的过电压可以启动测试模式。 测试模式使能信号可以通过设置在第二封装引脚上的信号锁存到其活动状态。 此后，第一和第二封装引脚可以在测试操作期间在正常电压范围内使用。

公开(公告)号：US5629943A

公开(公告)日：1997-05-13

申请号：US251565

申请日：1994-05-31

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C29/02 ,  G11C29/50 ,  G11C29/00

CPC classification number: G11C29/025 ,  G11C29/02 ,  G11C29/50 ,  G11C11/41

Abstract: Circuitry for performing a special test of an integrated memory circuit is disclosed, where the special test requires driving of both bitlines associated with a column of memory cells to a selected logic level, such as ground. The special test is performed in a mode different from normal operation of the memory, and is useful in performing a write disturb test, and in performing stress tests of memory elements such as pass transistors in static random access memory cells. The special test is performed by generating an internal signal selecting the placement of both bitlines in one or more bitline pairs to the selected logic level. Circuitry is also disclosed which uses the output enable terminal, in the special test mode, for controlling the driving of both bitlines to the selected logic level, as the output enable terminal otherwise has no required function in this special test mode.

Abstract translation: 公开了用于执行集成存储器电路的特殊测试的电路，其中特殊测试要求将与存储器单元列相关联的两个位线驱动到所选择的逻辑电平，例如地。 特殊测试以与​​存储器的正常操作不同的模式执行，并且在执行写入干扰测试以及在诸如静态随机存取存储器单元中的传输晶体管的存储器元件的压力测试中是有用的。 通过产生选择将一个或多个位线对中的两个位线放置到所选逻辑电平的内部信号来执行特殊测试。 还公开了电路，其在专用测试模式中使用输出使能端，用于将两个位线的驱动控制到所选择的逻辑电平，因为输出使能端子在该特殊测试模式中不具有所需功能。

公开(公告)号：US5629896A

公开(公告)日：1997-05-13

申请号：US521800

申请日：1995-08-31

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C7/10 ,  G11C8/06 ,  H03K3/012 ,  G11C7/00

CPC classification number: G11C7/1078 ,  G11C7/1051 ,  G11C8/06 ,  H03K3/012

Abstract: An input buffer, for an asynchronous integrated memory circuit incorporating a memory circuit, including a latch circuit controlled by a write enable signal is disclosed. The input stage of the input buffer is connected to a pass gate, which is controlled by the write enable signal so that the pass gate is nonconductive when the write enable signal is active. The output of the pass gate is connected to an input of the latch circuit. The latch circuit is controlled by the write enable signal so that the signal present on the input of the latch is latched when the write enable signal is active. From an output of the latch circuit are obtained true and complementary signals, which are applied to outputs of the buffer circuit. As a result, when the write enable signal is active, the signal present on the input of the buffer is latched and presented to the outputs of the buffer, and the latch circuit is isolated from the input of the buffer until the write cycle is terminated.

Abstract translation: 公开了一种用于包括由写使能信号控制的锁存电路的存储器电路的异步集成存储器电路的输入缓冲器。 输入缓冲器的输入级连接到通过写入使能信号控制的通过栅极，使得当使能信号有效时，通过栅极不导通。 传输门的输出端连接到锁存电路的输入端。 锁存电路由写使能信号控制，使得当写使能信号有效时，锁存器输入端存在的信号被锁存。 从锁存电路的输出获得真实和互补信号，这些信号被施加到缓冲电路的输出端。 结果，当写使能信号有效时，存在于缓冲器的输入端的信号被锁存并呈现给缓冲器的输出，并且锁存电路与缓冲器的输入隔离，直到写周期终止 。

公开(公告)号：US5627787A

公开(公告)日：1997-05-06

申请号：US367979

申请日：1995-01-03

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C8/12 ,  G11C29/02 ,  G11C29/50 ,  G11C7/00 ,  G11C29/00

CPC classification number: G11C29/024 ,  G11C29/02 ,  G11C29/50 ,  G11C8/12 ,  G11C11/41

Abstract: According to the method of the present invention, stress testing of decoders and other periphery circuits of synchronous RAMs is performed within a reasonable period of time and without an increase in the complexity of stress testing or fabrication of synchronous RAMs. In order to stress test decoders and periphery circuits of a synchronous RAM to obtain maximum fault coverage of possible latent defects, a periphery stress mode is defined through appropriate manipulation of the Power-On Reset signal of the device such that all nodes of a memory array of the synchronous RAM are pulled in the opposite logic state from that required for a memory cell stress mode. In the periphery stress mode, the Power-On Reset signal is allowed to pulse upon power-up of the synchronous RAM device such that latches and flip flops of the device are forced in a logic state that disables all rows and columns of the memory array of the device. Additionally, all D.C. (direct current) paths of the synchronous RAM are disabled so that a high power supply voltage may be applied during the periphery stress mode without fear of transistor "snap back voltage". Thus, once all D.C. paths of the synchronous RAM are disabled, a Vcc voltage level as high as ten volts may be applied during the periphery stress mode without experiencing transistor impact ionization due to high substrate current, known as BVDII or "snap back voltage".

Abstract translation: 根据本发明的方法，同步RAM的解码器和其它外围电路的压力测试在合理的时间段内进行，并且不增加压力测试或同步RAM的制造的复杂性。 为了压缩同步RAM的测试解码器和外围电路以获得可能的潜在缺陷的最大故障覆盖，通过适当地操纵器件的上电复位信号来定义外围应力模式，使得存储器阵列的所有节点 的同步RAM被拉到与存储单元压力模式所需的逻辑状态相反的逻辑状态。 在外围应力模式下，允许上电复位信号在同步RAM器件上电时脉冲，使得器件的锁存器和触发器被强制为禁止存储器阵列的所有行和列的逻辑状态 的设备。 此外，同步RAM的所有直流（直流）路径被禁用，使得可以在周边应力模式期间施加高电源电压，而不用担心晶体管“反电压”。 因此，一旦同步RAM的所有DC路径被禁止，则可以在周边应力模式期间施加高达十伏的Vcc电压电平，而不会由于高衬底电流（称为BVDII或“回跳电压”）而经历晶体管冲击电离， 。

公开(公告)号：US5619456A

公开(公告)日：1997-04-08

申请号：US588901

申请日：1996-01-19

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C7/10 ,  G11C13/00

CPC classification number: G11C7/106 ,  G11C7/1051 ,  G11C7/1072

Abstract: The time required to output data from an output buffer is significantly reduced by having a slave latch in a parallel connection with a master latch. Incoming data is stored in a master latch on a first phase of a clock pulse. On the second phase of the clock pulse, the data is output of the master latch and provided to an output driver. A slave latch is coupled to the input node of the output driver. On the subsequent phase of the clock, the slave latch is switched on to hold the state of the input to the output driver constant. The slave latch thus receives the output of the master register in parallel with the output driver and also performs its function of maintaining the input to the output buffer for one entire clock pulse while new data is being presented to the master latch. Data is thus provided more quickly to the output driver than was previously possible with prior art master/slave configurations.

Abstract translation: 通过使从锁存器与主锁存器并联连接，从输出缓冲器输出数据所需的时间显着减少。 传入数据存储在时钟脉冲的第一阶段的主锁存器中。 在时钟脉冲的第二阶段，数据是主锁存器的输出，并提供给输出驱动器。 从锁存器耦合到输出驱动器的输入节点。 在随后的时钟相位中，从锁存器被接通以将输入的状态保持在输出驱动器的恒定状态。 因此，从锁存器与输出驱动器并行地接收主寄存器的输出，并且还执行其将新数据呈现给主锁存器时将整个时钟脉冲的输入保持到输出缓冲器的功能。 因此，与现有技术的主/从配置的先前可能相比，数据比输出驱动器更快地被提供。

公开(公告)号：US5581209A

公开(公告)日：1996-12-03

申请号：US359927

申请日：1994-12-20

Applicant: David C. McClure

Inventor： David C. McClure

IPC: H03F3/343 ,  G05F3/26 ,  H03F3/347 ,  G05F1/10

CPC classification number: G05F3/262

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses. An offset compensating current source adds current into the reference leg of the current mirror to eliminate the development of an offset voltage in the current mirror, and the limited output high voltage is shifted by the threshold voltage of the pull-up drive transistor by way of a threshold shift circuit.

Abstract translation: 公开了一种用于集成电路的输出驱动器电路，其中输出驱动器驱动具有从集成电路的电源电压限制的电压的高逻辑电平的输出端子。 通过将有限的输出高电压施加到输出缓冲器来提供有限的电压，使得施加到输出驱动器中的上拉晶体管的栅极的驱动信号受到施加到输出缓冲器的受限输出高电压的限制。 还公开了用于产生有限输出高电压的电压基准和调节器电路，并且基于电流镜。 电流镜中的电流总和由偏置电流源控制，偏置电流源可以在运行周期内动态控制或通过熔丝进行编程。 偏移补偿电流源将电流加到电流镜的参考支路中，以消除电流镜中偏移电压的发展，并且受限输出高电压通过上拉驱动晶体管的阈值电压偏移 阈值移位电路。

公开(公告)号：US5572470A

公开(公告)日：1996-11-05

申请号：US438349

申请日：1995-05-10

Applicant: David C. McClure ,  Thomas Teel

Inventor： David C. McClure ,  Thomas Teel

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G11C29/80 ,  G11C29/808 ,  G11C29/84 ,  G11C29/846

Abstract: An apparatus maps one of a plurality of redundant memory columns, each having a redundant memory cell, to an address of a defective memory column in a memory device that communicates with an external data bus having one or more data-bit lines and an address bus. An address decoder receives an address signal on the address bus and generates an enable signal to enable the redundant cell of the redundant column when the value of the address signal equals the address of the defective memory column. A bit-select bus has one or more bit-select lines each associated with one of the data-bit lines. Each bit-select line can carry a bit-select signal. Each of a plurality of bit-line selectors is associated with one of the redundant columns and communicates with the bit-select bus. In response to an associated enable signal, each bit-line selector can generate the bit-select signal on the bit-select line associated with a desired data-bit line. An interface circuit couples the redundant cell to the desired data-bit line in response to the bit-select signal.

Abstract translation: 一种装置将具有冗余存储单元的多个冗余存储器列之一映射到与具有一个或多个数据位线和地址总线的外部数据总线进行通信的存储器件中的缺陷存储器列的地址 。 地址解码器在地址总线上接收地址信号，并且当地址信号的值等于有缺陷的存储器列的地址时，产生使能信号以使能冗余列的冗余单元。 位选择总线具有每个与数据位线之一相关联的一个或多个位选择线。 每个位选择行可以携带位选择信号。 多个位线选择器中的每一个与冗余列中的一个相关联，并与位选择总线通信。 响应于相关联的使能信号，每个位线选择器可以在与期望的数据位线相关联的位选择线上产生位选择信号。 接口电路响应于位选择信号将冗余单元耦合到期望的数据位线。

公开(公告)号：US5526318A

公开(公告)日：1996-06-11

申请号：US376127

申请日：1995-01-19

Applicant: William C. Slemmer ,  David C. McClure

Inventor： William C. Slemmer ,  David C. McClure

IPC: G11C11/41 ,  G11C8/08 ,  G11C8/18 ,  G11C11/401 ,  G11C16/06 ,  G11C17/00 ,  G11C7/00

CPC classification number: G11C8/18 ,  G11C8/08

Abstract: An integrated circuit memory is disclosed which has its memory array divided into blocks, or sub-arrays. Between each sub-array is placed a row line repeater which communicates the row line from the row decoder, or from a prior sub-array, into the next sub-array. The row line repeaters are controlled according to a portion of the column address so that, after the entire selected row has been energized, those row line repeaters which are not associated with the selected sub-array will de-energize the row line at their output. The row line repeaters each include a latch, so that the row line repeater which is associated with the selected sub-array will maintain the selected row line energized. Various embodiments of the row line repeater circuit are disclosed. Further control of the row line repeaters from a power-on reset circuit is also disclosed. A dummy row line is also disclosed, which emulates an actual row line so that the time at which the selected row has been fully energized is more closely known. The dummy row line thus can control the time at which the unselected row line repeaters de-energize their outputs.

Abstract translation: 公开了一种集成电路存储器，其存储器阵列分为块或子阵列。 在每个子阵列之间放置有行行中继器，其将来自行解码器的行线或从先前的子阵列传送到下一个子阵列。 根据列地址的一部分来控制行行中继器，使得在整个所选行被通电之后，与选择的子阵列不相关联的那些行行中继器将在其输出处的行线断电 。 行行中继器各自包括锁存器，使得与选择的子阵列相关联的行行中继器将保持所选择的行线路通电。 公开了行行中继器电路的各种实施例。 还公开了从上电复位电路对行行中继器的进一步控制。 还公开了虚拟行线，其模拟实际的行线，使得所选择的行已被完全通电的时间更为公知。 因此，虚拟行线可以控制未选择的行行中继器使其输出断电的时间。

公开(公告)号：US5493537A

公开(公告)日：1996-02-20

申请号：US202830

申请日：1994-02-28

Applicant: David C. McClure

Inventor： David C. McClure

IPC: G11C7/20 ,  G11C7/22 ,  G11C8/18 ,  G11C8/00

CPC classification number: G11C7/22 ,  G11C7/20 ,  G11C8/18

Abstract: A system and method are provided for disabling the edge transition detection circuit during the flash clear cycle, thereby preventing the generation of an edge transition detection pulse. In a preferred embodiment of the invention, the edge transition detection circuit is connected to the flash clear complement circuitry through a logic gate. During the flash clear cycle, flash clear true, FC.sub.T, is pulled high, flash clear complement, FC.sub.c, is pulled low and inverted to drive a portion of the ETD circuitry high, thereby preventing generation of an ETD pulse during the flash clear cycle.

Abstract translation: 提供了一种用于在闪光清除周期期间禁止边沿跃迁检测电路的系统和方法，从而防止产生边沿跃迁检测脉冲。 在本发明的优选实施例中，边缘跃迁检测电路通过逻辑门连接到闪光补偿电路。 在闪光清除周期期间，闪烁清零，FCT被拉高，闪烁补充，FCc被拉低并反相，以将ETD电路的一部分驱动为高电平，从而防止在闪烁清除周期期间产生ETD脉冲。