Abstract:
A saw table apparatus comprises a table and a saw mounting structure. The table includes a base and a tabletop attached to the base. The tabletop has a work-piece support surface. The saw mounting structure is engaged with the tabletop. The saw mounting structure is configured for having a hand-held circular saw attached thereto such that, when the saw mounting structure is in a use position with respect to the tabletop, a blade of the hand-held circular saw extends above a work-piece support surface of the tabletop and a work-piece engagement surface of the saw mounting structure lies substantially flush with the work-piece support surface of the tabletop. An engagement portion of the electrical plug receptacle is expose within an interior space of the base and a control portion of the electrical switch is exposed an exterior surface of the base.
Abstract:
A latch circuit 2 is described including a function path latch 4, 6, which may be in the form of a standard flip-flop, together with a data retention latch 12, 14. The reset signal nreset and the scan enable signal SE are used to control these latches to perform reset, scan, save and restore functions. The save and restore functions serve to save a data value dv from the functional path latch 4, 6 into the data retention latch 12, 14 and restore this value such that the functional path latch can be powered down without a loss of data.
Abstract:
According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited in a deposition process using an ammonia-to-silane ratio of at least 12.5. The method further includes depositing a layer of MIM capacitor metal on the layer of silicon nitride. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the method further includes etching the layer of silicon nitride to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor. The MIM capacitor has a capacitance density of at least 2.0 fF/um2.
Abstract:
According to a disclosed embodiment, a composite MIM capacitor comprises a lower electrode of a lower MIM capacitor situated in a lower interconnect metal layer of a semiconductor die. The composite MIM capacitor further comprises an upper electrode of the lower MIM capacitor situated within a lower interlayer dielectric, where the lower interlayer dielectric separates the lower interconnect metal layer from an upper interconnect metal layer. A lower electrode of the upper MIM capacitor is situated in the upper interconnect metal layer. An upper electrode of the upper MIM capacitor is situated within the upper interlayer dielectric which is, in turn, situated over the upper interconnect metal layer. The upper electrode of the lower MIM capacitor is connected to the lower electrode of the upper MIM capacitor while the lower electrode of the lower MIM capacitor is connected to the upper electrode of the upper MIM capacitor.
Abstract:
According to one exemplary embodiment, an NPN bipolar transistor comprises a base layer situated over a collector, where the base layer comprises an intrinsic base region and an extrinsic base region. The NPN bipolar transistor may be, for example, an NPN silicon-germanium heterojunction bipolar transistor. The base layer can be, for example, silicon-germanium. According to this exemplary embodiment, the NPN bipolar transistor further comprises a cap layer situated over the base layer, where a portion of the cap layer is situated over the extrinsic base region, and where the portion of the cap layer situated over the extrinsic base region comprises an indium dopant. The cap layer may be, for example, polycrystalline silicon. According to this exemplary embodiment, the NPN bipolar transistor may further comprise an emitter situated over the intrinsic base region. The emitter may be, for example, polycrystalline silicon.
Abstract:
A general purpose method is provided for interfacing with a storage device having a tape medium. The method includes receiving data from a first source, and creating a first data packet having at least a portion of the data from the first source. The method also includes receiving data from a second source, and creating a second data packet having at least a portion of the data from the second source. The method further includes receiving additional data from the first source, and creating a third data packet having at least a portion of the additional data from the first source. The method still further includes transmitting the first data packet, the second data packet and the third data packet to the storage device, and storing the first data packet, the second data packet, and the third data packet on the tape medium in an interleaved configuration. A system including control logic is also provided for performing the method.
Abstract:
A method is provided for interfacing with a storage device having a tape medium. The method includes receiving data from a first source, and creating a first data packet having at least a portion of the data from the first source. The method also includes receiving data from a second source, and creating a second data packet having at least a portion of the data from the second source. The method further includes receiving additional data from the first source, and creating a third data packet having at least a portion of the additional data from the first source. The method still further includes transmitting the first data packet, the second data packet and the third data packet to the storage device, and storing the first data packet, the second data packet, and the third data packet on the tape medium in an interleaved configuration. A system including control logic is also provided for performing the method.
Abstract:
An apparatus, a loop burner element, and a method for surface-roasting a food product wherein the roasting apparatus comprises (a) a conveyor which carries the food product and (b) at least one non-linear ribbon flame burner element or element assembly which preferably applies a ribbon flame to at least the upper and side surfaces of the food product as it is conducted through the roasting apparatus.
Abstract:
An apparatus and method for continuously searing and/or branding the surface of and continuously cooking a food product wherein the cooking oven is different from the searing and/or branding apparatus. At least a portion of the vapor product produced in the searing and/or branding apparatus is preferably delivered into the oven such that the food product is cooked in an environment comprising the vapor product from the searing and/or branding apparatus. The vapor extraction rate from the searing and/or branding apparatus is also preferably controlled to maintain a desired vapor product temperature in or flowing from the searing and/or branding apparatus.
Abstract:
A process for producing precooked bacon slices comprising the steps of (a) conveying bacon slices through a spiral oven, (b) indirectly cooking the bacon slices in the spiral oven using a cooking medium which is circulated within the oven at a low rate sufficient to prevent the bacon slices from being displaced on the conveyor, and (c) adding steam to the cooking medium as necessary to at least reduce the percentage or substantially eliminate the presence of air in the cooking medium.