公开(公告)号：US06559703B1

公开(公告)日：2003-05-06

申请号：US09607460

申请日：2000-06-29

申请人： David Kwong ,  Eddie Siu Yam Chan

发明人： David Kwong ,  Eddie Siu Yam Chan

IPC分类号： H03K190175

CPC分类号： H03K17/165

摘要： A bus switch is protected from undershoots on either of its terminals. The bus switch transistor is an n-channel metal-oxide-semiconductor (MOS) with its source connected to a first bus and its drain connected to a second bus. During isolation, the gate node of the bus switch transistor is discharged to ground by a pulsed transistor, and then kept at ground by a leaker transistor. Sense-pulse circuits are attached to the first and second bus. When a low-going transition is detected by a sense-pulse circuit, an n-channel connecting transistor is turned on, connecting the bus with the low-going transition to the gate node through a grounded-gate n-channel transistor. If an undershoot occurs, it is coupled to the gate node. Since both the gate and source of the bus switch transistor are coupled to the undershoot, the gate-to-source voltage never reaches the transistor threshold and the bus switch transistor remains off. An external direction signal may also be used to pre-activate the connecting transistor for one of the two sides of the bus switch transistor, replacing the sense-pulse circuits.

摘要翻译： 一个总线开关可以防止其任何一个端子的下冲。 总线开关晶体管是n沟道金属氧化物半导体（MOS），其源极连接到第一总线，其漏极连接到第二总线。 在隔离期间，总线开关晶体管的栅极节点由脉冲晶体管放电到地，然后由漏电晶体管保持接地。 感测脉冲电路连接到第一和第二总线。 当由感测脉冲电路检测到低电平转换时，n沟道连接晶体管导通，通过接地栅极n沟道晶体管将总线与低电平跃迁连接到栅极节点。 如果发生下冲，则耦合到门节点。 由于总线开关晶体管的栅极和源极都耦合到下冲，栅极至源极电压不会达到晶体管阈值，并且总线开关晶体管保持关断。 也可以使用外部方向信号来预先激活用于总线开关晶体管的两侧之一的连接晶体管，代替感测脉冲电路。

公开(公告)号：US06525559B1

公开(公告)日：2003-02-25

申请号：US10063416

申请日：2002-04-22

申请人： Ke Wu ,  David Kwong

发明人： Ke Wu ,  David Kwong

IPC分类号： H03K19003

CPC分类号： H04L25/08 ,  H03K19/007

摘要： A fail-safe circuit for a pair of differential input lines detects when one or both lines are open. Each line has a pull-up of a switched p-channel transistor in series with a resistor or another p-channel transistor that has its effective resistance controlled by a gate bias. The gate of the switched p-channel transistor is driven to ground when power is applied to the gate of a grounding n-channel transistor. When power is off, a p-channel connecting transistor charges the gate node from the differential input line when a positive voltage is applied to the input line, such as during a leakage test. Charging the gate node prevents the switched p-channel transistor from turning on, blocking a leakage current path through the pull-up. An N-well bias circuit can be added, which connects the N-well under p-channel transistors to power or the gate node or the input line.

摘要翻译： 一对差分输入线的故障安全电路检测一条或两条线是否断开。 每行具有与电阻器或具有由栅极偏置控制的其有效电阻的另一p沟道晶体管串联的开关p沟道晶体管的上拉电阻。 当电源施加到接地n沟道晶体管的栅极时，开关p沟道晶体管的栅极被驱动到地。 当电源关闭时，例如在泄漏测试期间，当正电压施加到输入线时，p沟道连接晶体管将来自差分输入线的栅极节点充电。 对栅极节点进行充电可防止开关的p沟道晶体管导通，阻止通过上拉的漏电流路径。 可以添加N阱偏置电路，其将p沟道晶体管下的N阱连接到电源或栅极节点或输入线。

公开(公告)号：US06486727B1

公开(公告)日：2002-11-26

申请号：US09682736

申请日：2001-10-11

申请人： David Kwong

发明人： David Kwong

IPC分类号： H03K301

CPC分类号： H02M3/073 ,  H02M2001/0022 ,  H02M2001/0041

摘要： A substrate bias generator has a ring oscillator disabled when a supply over-voltage condition is detected by a supply comparator, or when a target substrate voltage is reached. A substrate comparator compares the substrate voltage to a reference generated by a p-channel sense transistor that is independent of the substrate voltage. The substrate is sensed by an n-channel sense transistor with only its bulk connected to the substrate voltage. Current sources for the sense transistors and comparator are controlled by bias voltages generated by a voltage divider that switches from a high-power state to a low-power state once the substrate target is reached. Feedback turns off a high-current resistor, limiting current to that passing through a low-current resistor. The bias voltages are adjusted to reduce current to the sense transistors and comparator, reducing power. High current and power are used for fast sensing before the substrate target is reached.

摘要翻译： 当供电比较器检测到供电过电压条件时，或当达到目标衬底电压时，衬底偏置发生器使环形振荡器无效。 衬底比较器将衬底电压与由p沟道读出晶体管产生的参考值进行比较，该参考晶体管独立于衬底电压。 衬底由n沟道感测晶体管感测，其仅其体积连接到衬底电压。 感测晶体管和比较器的电流源通过分压器产生的偏置电压来控制，该分压器一旦达到衬底靶，则从高功率状态切换到低功率状态。 反馈关闭大电流电阻，限制电流通过低电流电阻。 偏置电压被调整以减少到感测晶体管和比较器的电流，从而降低功率。 在达到基板目标之前，高电流和高功率用于快速感测。

公开(公告)号：US06583659B1

公开(公告)日：2003-06-24

申请号：US09683744

申请日：2002-02-08

申请人： David Kwong ,  Kwong Shing Lin

发明人： David Kwong ,  Kwong Shing Lin

IPC分类号： G06F104

CPC分类号： G06F1/10

摘要： A clock driver chip has several banks of clock outputs driven by a single clock reference. Each clock output is driven by large pull-up and pull-down transistors, which have gates driven by pre-driver lines generated by a pre-driver circuit. Individual clock outputs, or a bank of outputs, are enabled by enable signals. A shorting switch is activated when enables for a pair of clock outputs are in a same state. The shorting switch has two transmission gates. One transmission gate shorts the pre-driver lines to the large p-channel transistors of the pair of outputs, while the other transmission gate shorts the pre-driver lines to the large n-channel transistors of the pair of outputs. Pre-driver lines to the pull-up transistors within a bank driven by the same enable can be hardwired together, as can the pre-driver lines to the pull-down transistors. Shorting switches can short banks together to reduce output skew.

摘要翻译： 时钟驱动器芯片具有由单个时钟参考驱动的多组时钟输出。 每个时钟输出由大的上拉和下拉晶体管驱动，其具有由预驱动器电路产生的预驱动线驱动的门。 单个时钟输出或一组输出通过使能信号使能。 当一对时钟输出处于相同状态时，启用短路开关。 短路开关有两个传输门。 一个传输门将预驱动器线路短路到一对输出的大的p沟道晶体管，而另一个传输栅极将预驱动器线路短路到该对输出的大的n沟道晶体管。 通过相同使能驱动的组内的上拉晶体管的预驱动线可以一起硬连线，以及预驱动器线到下拉晶体管。 短路开关可以将组合短路以减少输出偏移。

公开(公告)号：US06424217B1

公开(公告)日：2002-07-23

申请号：US09682459

申请日：2001-09-05

申请人： David Kwong

发明人： David Kwong

IPC分类号： H03F345

CPC分类号： H03K19/1738 ,  H03K19/0016 ,  H03K19/018528

摘要： A differential amplifier has a boosted sink current that is turned on by a pulse generator when the output is driven low. This boosted sink current quickly lowers the output to the voltage-output-low VOL level. After the pulse ends, the sink current ends and power is reduced to a lower standby level. A differential pair of switches receives the true and complement data. One switch is closed when the data is true, connecting a current source that sets the standby voltage-output-high VOH level. The other switch is closed when the complement data is high, connecting another current source that sets the standby VOL level. A second differential amplifier with reversed true and complement data drives a complement output for a differential signaling transmitter, such as for a pseudo-emitter-coupled logic (PECL) driver.

摘要翻译： 差分放大器具有升压的灌电流，当输出被驱动为低电平时，脉冲发生器导通。 该升压的灌电流快速将输出降低到电压 - 输出 - 低VOL电平。 脉冲结束后，接收器电流结束，电源降低到待机电平较低。 一对差分开关接收真实数据和补码数据。 当数据为真时，一个开关闭合，连接设置备用电压输出高VOH电平的电流源。 当补码数据为高电平时，另一个开关闭合，连接设置待机VOL电平的另一个电流源。 具有反向真和补数据的第二个差分放大器驱动差分信号发送器的补码输出，例如伪发射极耦合逻辑（PECL）驱动器。

公开(公告)号：US06288584B1

公开(公告)日：2001-09-11

申请号：US09679746

申请日：2000-10-05

申请人： Ke Wu ,  David Kwong

发明人： Ke Wu ,  David Kwong

IPC分类号： H03K1722

CPC分类号： H03K17/223

摘要： A power-up-reset circuit draws zero standby current. Rather than use a voltage divider that always draws current, a capacitive-pullup divider is used as the first stage. The capacitive-pullup divider has a capacitor to power (Vcc) and n-channel series transistors to ground. A sensing node between the capacitor and n-channel series transistors is initially pulled high to Vcc as Vcc is ramped up. The n-channel transistors remain off until Vcc reaches about 1.5 volts. Then the n-channel transistors pull the sensing node quickly to ground, ending the reset pulse. The second stage has a capacitor to ground that initially holds a threshold node low. A p-channel transistor has a gate connected to the sensing node and charges up the capacitor when the sensing node falls to ground. A third stage is triggered to change state as the capacitor is charged up by the p-channel transistor. Then a Schmidt trigger toggles, as do downstream inverter stages. A feedback signal goes low, disabling the gate of a pulldown n-channel transistor in the second stage. This disables a power-to-ground current path.

摘要翻译： 上电复位电路吸收零待机电流。 不是使用总是吸引电流的分压器，而是使用电容上拉分压器作为第一级。 电容上拉分压器具有电容（Vcc）和n沟道串联晶体管接地。 电容器和n沟道串联晶体管之间的感测节点最初被拉高到Vcc，因为Vcc是斜坡上升的。 n沟道晶体管保持截止，直到Vcc达到约1.5伏。 然后，n沟道晶体管将感测节点快速拉到地，结束复位脉冲。 第二级具有初始保持阈值节点低的接地电容。 p沟道晶体管具有连接到感测节点的栅极，并且当感测节点落地时对电容器充电。 当电容器被p沟道晶体管充电时，第三级被触发以改变状态。 那么施密特触发器就会切换，下游的逆变器阶段也是如此。 反馈信号变为低电平，禁用第二级中的下拉式n沟道晶体管的栅极。 这将禁用电源对地电流路径。

公开(公告)号：US6118640A

公开(公告)日：2000-09-12

申请号：US251722

申请日：1999-02-17

申请人： David Kwong

发明人： David Kwong

IPC分类号： H01L27/02 ,  H02H9/04 ,  H02H9/00

CPC分类号： H01L27/0248 ,  H02H9/046

摘要： An electro-static-discharge (ESD) protection circuit protects internal power supplies in a mixed-signal IC. An active protection circuit is used. The ESD-protection circuit uses standard transistors and is actively enabled and disabled by standard transistors. A standard thin-oxide NMOS transistor is the ESD switch (shunt) between power supply busses. This thin-oxide transistor ESD switch is actively enabled and disabled by a control circuit. NMOS transistors in the control circuit discharge the gate node of the ESD switch when the power supplies are powered up, thus actively disabling the ESD protection circuit. When an ESD pulse is applied to a supply when powered down, a capacitor couples the rapid voltage rise to the gate node. The rising voltage turns on the ESD switch, shunting the ESD pulse to the other supply. A resistor and a p-channel MOS transistor in series then discharge the gate node to the other supply. The capacitor, resistor, and p-channel transistor form an RC network. A second RC network is connected to the other supply so that symmetric protection is provided. Slow and unresponsive thick-oxide transistors and diodes are avoided.

摘要翻译： 静电放电（ESD）保护电路保护混合信号IC中的内部电源。 使用主动保护电路。 ESD保护电路使用标准晶体管，并被标准晶体管主动使能和禁用。 标准的薄氧化物NMOS晶体管是电源总线之间的ESD开关（分流）。 该薄氧化物晶体管ESD开关由控制电路主动使能和禁止。 当电源供电时，控制电路中的NMOS晶体管对ESD开关的栅极节点放电，从而主动禁用ESD保护电路。 当掉电时将ESD脉冲施加到电源时，电容将快速电压上升耦合到栅极节点。 上升电压打开ESD开关，将ESD脉冲分流到另一个电源。 串联的电阻器和p沟道MOS晶体管将栅极节点放电到另一个电源。 电容器，电阻和p沟道晶体管形成RC网络。 第二个RC网络连接到另一个电源，从而提供对称保护。 避免了缓慢且无响应的厚氧化物晶体管和二极管。

公开(公告)号：US5717343A

公开(公告)日：1998-02-10

申请号：US685142

申请日：1996-07-23

申请人： David Kwong

发明人： David Kwong

IPC分类号： H03K19/003 ,  H03K19/0948 ,  H03K17/16

CPC分类号： H03K19/00361

摘要： A CMOS output buffer has a first stage with smaller driver transistors and a second stage having larger driver transistors. Both stages drive the output in parallel during the first half of a voltage transition, but the larger, second stage is disabled during the second half of the output voltage swing. The output voltage is fed back to an isolation circuit by a pulse generator which is triggered by the output reaching the switching threshold. The pulse generated disables the larger driver for a short period of time but later re-enables the driver. Thus the large driver remains on after the switching is complete, providing large IOH and IOL static currents. The pulse is long enough to keep the large driver disabled while reflections are received and ringing occurs after the voltage transition. Resistors in the smaller first stage absorb these reflections. The output impedance is pulsed to the higher impedance of the first stage when ringing occurs at the end of the voltage transition, but after the pulse ends the lower impedance of the large driver is seen. Pulses are sent to neighboring output buffers and are OR'ed together to disable adjacent output buffer's large drivers when noise in injected into the power or ground supplies.

摘要翻译： CMOS输出缓冲器具有第一级，具有较小的驱动晶体管，第二级具有较大的驱动晶体管。 两个级在电压转换的前半部分并联驱动输出，但在输出电压摆幅的后半段期间，较大的第二级被禁止。 输出电压通过脉冲发生器反馈到隔离电路，脉冲发生器由输出触发，达到切换阈值。 生成的脉冲会在较短的时间内禁用较大的驱动程序，但稍后重新启用驱动程序。 因此，在开关完成后，大的驱动器保持接通，从而提供大的IOH和IOL静电流。 脉冲长度足以保持大驱动器禁用，同时接收反射并在电压转换后发生振铃。 较小的第一阶段的电阻吸收这些反射。 当在电压转换结束时发生振铃时，输出阻抗被脉冲到第一级的较高阻抗，但是在脉冲结束之后，看到大驱动器的较低阻抗。 脉冲被发送到相邻的输出缓冲器，并且当被注入到电源或地面电源中的噪声时被对齐在一起以禁用相邻输出缓冲器的大驱动器。

公开(公告)号：US5444397A

公开(公告)日：1995-08-22

申请号：US318238

申请日：1994-10-05

申请人： Anthony Y. Wong ,  David Kwong ,  Lee Yang ,  Charles Hsiao

发明人： Anthony Y. Wong ,  David Kwong ,  Lee Yang ,  Charles Hsiao

IPC分类号： H03K19/00 ,  H01L27/02 ,  H01L27/118 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0948 ,  H03K19/02

CPC分类号： H03K19/00315 ,  H01L27/0218 ,  H01L27/11898 ,  H03K2217/0018

摘要： An all-CMOS output buffer drives a bus that can operate at 3 volts and 5 volts. When in a high-impedance state, the output buffer draws little or no current. If the bus is driven to 5 volts by an external device, the high impedance output buffer is in danger of latch-up and distortion of the bus logic level since it only has a 3-volt power supply and does not use a charge pump or an extra 5-volt supply. A biasing circuit couples an N-well that contains p-channel transistors and a driver transistor to the bus driven to 5 volts. Thus the N-well is also driven to 5 volts, the voltage on the bus. The gate of the p-channel driver transistor in the high-impedance output buffer is also coupled to the N-well by another p-channel transistor, raising the gate potential to 5 volts. Thus the gate and body of the p-channel driver transistor is at 5 volts, eliminating reversing current and latch-up problems. A transmission gate isolates the gate of the p-channel driver transistor from the rest of the device's circuitry. The p-channel transistors of the transmission gate, bias circuitry, and driver transistor are located in the N-well, which is biased up to 5 volts only when necessary. Thus during normal operation, the N-well of the driver transistor is at 3 volts, eliminating a performance loss from the body effect. A logic gate increases the well bias and isolates the driver's gate only when necessary, when the bus is high and driven by a 5-volt device, and the output buffer is in high-impedance.

摘要翻译： 全CMOS输出缓冲器驱动可在3伏和5伏电压下工作的总线。 当处于高阻抗状态时，输出缓冲器很少或没有电流。 如果总线通过外部设备驱动到5伏特，则高阻抗输出缓冲器可能会因总线逻辑电平而产生闩锁和失真，因为它只有3伏电源，不使用电荷泵或 额外的5伏电源。 偏置电路将包含p沟道晶体管的N阱和驱动晶体管耦合到被驱动到5伏特的总线。 因此，N阱也被驱动到5伏，即总线上的电压。 高阻抗输出缓冲器中的p沟道驱动晶体管的栅极也通过另一个p沟道晶体管耦合到N阱，将栅极电位提高到5伏。 因此，p沟道驱动晶体管的栅极和体是5伏特，消除了反向电流和闭锁问题。 传输门将p沟道驱动晶体管的栅极与器件电路的其余部分隔离。 传输门，偏置电路和驱动晶体管的p沟道晶体管位于N阱中，仅在必要时才被偏置到5伏特。 因此，在正常工作期间，驱动晶体管的N阱处于3伏特，消除了体内效应的性能损失。 逻辑门增加了阱偏压，只有当必要时才能将驱动器门隔离，当总线为高电平并由5伏器件驱动时，输出缓冲器处于高阻态。

公开(公告)号：US07996806B2

公开(公告)日：2011-08-09

申请号：US12027146

申请日：2008-02-06

申请人： David Kwong

发明人： David Kwong

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5077 ,  H05K1/116 ,  H05K3/0005 ,  H05K3/429 ,  H05K2201/094 ,  H05K2201/09454

摘要： Methods and apparatus are provided for designing and laying out multi-layer circuit substrates, such as multi-layer PCBs. Dynamic vias are provided on intermediate PCB layers. Each dynamic via has features that adjust based on the trace layout of the corresponding intermediate layer. In particular, each dynamic via has a second radius R2 if the via is not connected to any trace on the corresponding intermediate layer. If a trace is connected to a dynamic via, the via radius changes from the second radius R2 to a first radius R1, where R1 is greater than R2.

摘要翻译： 提供了用于设计和布置多层电路基板（例如多层PCB）的方法和装置。 在中间PCB层上提供动态通孔。 每个动态通道具有根据相应中间层的跟踪布局进行调整的功能。 特别地，如果通孔不连接到相应中间层上的任何迹线，则每个动态通孔具有第二半径R2。 如果迹线连接到动态通孔，则通孔半径从第二个半径R2变为第一个半径R1，其中R1大于R2。