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公开(公告)号：US07890706B2
公开(公告)日：2011-02-15
申请号：US10990151
申请日：2004-11-16
IPC分类号： G06F13/14
CPC分类号： G06F11/1658 , G06F9/52 , G06F11/1641 , G06F11/1645 , G06F11/165 , G06F11/1683 , G06F11/1687 , G06F11/184 , G06F11/185 , G06F11/3404 , G06F11/3476 , G06F11/3495 , G06F11/3636 , G06F11/366 , G06F2201/88
摘要： In a system including multiple-slice processors and memories, a synchronization unit with race avoidance capability includes a delegated write engine that receives data and memory address information from the processors and writes data to the memory as a delegate for the processors.
摘要翻译： 在包括多片处理器和存储器的系统中，具有竞争回避能力的同步单元包括委托写入引擎，其从处理器接收数据和存储器地址信息，并将数据作为处理器的代理将数据写入存储器。
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12.发明授权System and method for implementing error detection and recovery in a system area network 有权在系统区域网络中实现错误检测和恢复的系统和方法公开(公告)号：US06545981B1
公开(公告)日：2003-04-08
申请号：US09224115
申请日：1998-12-30
IPC分类号： H04L1256
CPC分类号： H04L29/06 , G06F12/023 , G06F12/0292 , G06F12/1081 , H04L1/16 , H04L1/188 , H04L1/22 , H04L49/25 , H04L49/351 , H04L49/555 , H04L49/90 , H04L69/26 , H04L69/326
摘要： A system and method for facilitating both in-order and out-of-order packet reception in a SAN includes requestor and responder nodes, coupled by a plurality of paths, that maintain the good and bad status of each path and also maintain local copies of a message sequence number. If an error occurs for a transaction over a given path, the requestor informs the responder, over a good path, that the given path has failed and both nodes update their path status to indicate that the given path is bad. A barrier transaction is used by the requestor to determine whether the error is transient or permanent, and, if the error is transient, the requestor retries the transaction.
摘要翻译： 一种用于促进SAN中有序和无序分组接收的系统和方法包括通过多个路径耦合的请求者和响应者节点，其保持每个路径的良好和不良状态，并且还保持 一个消息序列号。 如果给定路径上的事务发生错误，则请求者通过良好的路径通知响应者给定路径失败，并且两个节点都更新其路径状态，以指示给定的路径不正确。 请求者使用屏障事务来确定错误是暂时的还是永久的，如果错误是短暂的，请求者重试事务。
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13.发明授权System and method for implementing multi-pathing data transfers in a system area network 有权在系统区域网络中实现多路径数据传输的系统和方法公开(公告)号：US06493343B1
公开(公告)日：2002-12-10
申请号：US09224114
申请日：1998-12-30
申请人： David J. Garcia , Richard O. Larson
发明人： David J. Garcia , Richard O. Larson
IPC分类号： H04L1228
CPC分类号： H04L49/30 , G06F12/023 , G06F12/0292 , G06F12/1081 , H04L1/16 , H04L1/188 , H04L1/22 , H04L29/06 , H04L49/557 , H04L49/90 , H04L69/26 , H04L69/324 , H04L69/326
摘要： A system and method for facilitating both in-order and out-of-order packet reception in a SAN includes requester and responder nodes that maintain local copies of a message sequence number. Each request packet includes an ordering field specifying whether the packets must be received in-order. The request node includes a copy of the local sequence number in each packet transmitted and increments its local copy of the sequence number only for packets that must be received in order. The responder node includes the received message sequence number in all response packets and increments its local copy of the message sequence number only if the ordering field specifies that the packets must be received in order.
摘要翻译： 一种用于促进SAN中的顺序和无序分组接收的系统和方法包括维护消息序列号的本地副本的请求者和响应者节点。 每个请求分组包括一个排序字段，指定分组是否必须按顺序接收。 请求节点包括发送的每个分组中的本地序列号的副本，并且仅对于必须按顺序接收的分组递增其序列号的本地副本。 响应者节点在所有响应分组中包括接收到的消息序列号，并且只有当排序字段指定必须按顺序接收分组时，才增加其消息序列号的本地副本。
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公开(公告)号：US20130313813A1
公开(公告)日：2013-11-28
申请号：US13898456
申请日：2013-05-20
IPC分类号： B60S9/04
摘要： A travel trailer stabilizing system having a right and left compound above-axle strut for bracing the trailer body at the axle or axles, each compound strut having an overlever arm for applying a stiffening force with a mechanical advantage to oppose any oscillatory motion of the frame on the tires. The mechanical advantage of the lever is configured to transfer a part of the weight of the trailer from the tires to the rigid struts.
摘要翻译： 一种旅行拖车稳定系统，其具有用于在车轴或车轴处支撑拖车车身的左右复合上轴支柱，每个复合支柱具有用于施加具有机械优点的加强力的超车臂，以抵抗框架的任何振荡运动 在轮胎上 杠杆的机械优点被配置成将拖车的重量的一部分从轮胎转移到刚性支柱。
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公开(公告)号：US07171484B1
公开(公告)日：2007-01-30
申请号：US09980759
申请日：2000-05-24
IPC分类号： G06F15/16
CPC分类号： H04L47/10 , G06F9/544 , H04L47/18 , H04L47/2475 , H04L47/34
摘要： A distributed computer system includes a source endnode including a source process which produces message data and a send work queue having work queue elements that describe the message data for sending. A destination endnode includes a destination process and a receive work queue having work queue elements that describe where to place incoming message data. A communication fabric provides communication between the source endnode and the destination endnode. An end-to-end context is provided at the source endnode and the destination endnode storing state information to ensure the reception and sequencing of message data sent from the source endnode to the destination endnode permitting reliable datagram service between the source endnode and the destination endnode.
摘要翻译： 分布式计算机系统包括源端节点，其包括产生消息数据的源过程和具有描述用于发送的消息数据的工作队列元素的发送工作队列。 目的地节点包括目的地进程和具有描述入站消息数据的位置的工作队列元素的接收工作队列。 通信结构提供源端节点和目的端节点之间的通信。 在源端节点和目的地端节点提供端到端上下文存储状态信息，以确保从源端节点发送到目的端点的消息数据的接收和排序，从而允许源端节点与目的端节点之间的可靠数据报服务 。
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16.发明授权
公开(公告)号：US06163834A
公开(公告)日：2000-12-19
申请号：US228069
申请日：1998-12-30
申请人： David J. Garcia , Daniel L. Fowler
发明人： David J. Garcia , Daniel L. Fowler
CPC分类号： H04L29/06 , G06F12/023 , G06F12/0292 , G06F12/1081 , H04L1/16 , H04L1/188 , H04L1/22 , H04L49/3009 , H04L49/351 , H04L49/90 , H04L69/26 , H04L69/326
摘要： A two-level memory region registration and address translation method includes a memory handle table and a translation and protection table (TPT). Each memory region registered is associated with a unique memory handle index which accesses one entry of the memory handle table. The accessed entry in the memory handle table stores a memory handle that is combined with virtual addresses in the registered memory region to access TPT entries storing translation data for the virtual addresses in the registered memory region.
摘要翻译： 二级存储器区域注册和地址转换方法包括存储器句柄表和转换和保护表（TPT）。 注册的每个存储器区域与访问存储器句柄表的一个条目的唯一存储器句柄索引相关联。 存储器句柄表中的访问条目存储与注册的存储器区域中的虚拟地址组合的存储器句柄，以访问存储注册存储器区域中的虚拟地址的转换数据的TPT条目。
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公开(公告)号：US5948111A
公开(公告)日：1999-09-07
申请号：US271238
申请日：1994-07-06
申请人： Mark A. Taylor , David J. Garcia , Paul A. Duffy
发明人： Mark A. Taylor , David J. Garcia , Paul A. Duffy
CPC分类号： H03K5/26 , G06F1/12 , G06F11/1679 , H03D13/004 , G06F11/1654 , G06F11/1695
摘要： A pair of substantially identical integrated circuit elements, in the form of microprocessors, are operated in response to the same instruction and data signals that are accessed from a memory by one of the integrated circuits. The accessed instruction and data signal are supplied, via a synchronous interface, to the second integrated circuit, which operates thinking that the supplied data and instruction signals were accessed by it in response to address and control signals. The states of the two integrated circuits are applied to comparator circuitry, both via buffered paths. The comparator circuitry is operated in response to control signals produced by the first integrated circuit to effect comparison on only those signals that are valid at any particular moment in time. Clock-synchronizing circuitry is included to ensure that predetermined state transitions of the clocks used to operate the first and second integrated circuit occur within a prescribed time period.
摘要翻译： 微处理器形式的一对基本上相同的集成电路元件响应于由集成电路之一从存储器访问的相同指令和数据信号而被操作。 所访问的指令和数据信号通过同步接口被提供给第二集成电路，该第二集成电路操作认为所提供的数据和指令信号是由其响应于地址和控制信号而被访问的。 两个集成电路的状态通过缓冲路径应用于比较器电路。 比较器电路响应于由第一集成电路产生的控制信号进行操作，以仅对在任何特定时刻有效的那些信号进行比较。 包括时钟同步电路以确保用于操作第一和第二集成电路的时钟的预定状态转换在规定时间段内发生。
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公开(公告)号：US5455935A
公开(公告)日：1995-10-03
申请号：US219152
申请日：1994-03-29
申请人： Mark A. Taylor , David J. Garcia , Paul A. Duffy
发明人： Mark A. Taylor , David J. Garcia , Paul A. Duffy
CPC分类号： H03K5/26 , G06F1/12 , G06F11/1679 , H03D13/004 , G06F11/1654 , G06F11/1695
摘要： A clock synchronization system includes a clock generator for producing first and second system clock signals that are each received by corresponding ones of a pair of integrated circuits from which the integrated circuits each produce secondary clock signals. The clock system includes synchronizing circuitry that receives the secondary clock signals to determine the phase difference between them, and delaying one of the system clock signals, relative to the other, in a manner that results in the state transitions of the secondary clock signals occur within a period of time of each other.
摘要翻译： 时钟同步系统包括用于产生第一和第二系统时钟信号的时钟发生器，每个时钟信号各自由集成电路各自产生辅助时钟信号的一对集成电路中的相应集成电路接收。 时钟系统包括同步电路，其接收次级时钟信号以确定它们之间的相位差，并以导致次级时钟信号的状态转换发生在其中的相对于另一个的方式延迟系统时钟信号之一 一段时间彼此。
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公开(公告)号：US20140353942A1
公开(公告)日：2014-12-04
申请号：US14461386
申请日：2014-08-16
摘要： A travel trailer stabilizing system having a right and left compound above-axle strut for bracing a trailer body at the axle or axles, each compound strut having an overlever arm for applying a stiffening force with a mechanical advantage to oppose any oscillatory motion of the frame on the tires. The mechanical advantage of the lever is configured to transfer a part of the weight of the trailer from the tires to the rigid struts.
摘要翻译： 一种旅行拖车稳定系统，其具有用于在车轴或车轴处支撑拖车车身的左右复合上轴支柱，每个复合支柱具有用于施加具有机械优点的加强力以抵抗框架的任何振荡运动的超车臂 在轮胎上 杠杆的机械优点被配置成将拖车的重量的一部分从轮胎转移到刚性支柱。
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公开(公告)号：US07565504B2
公开(公告)日：2009-07-21
申请号：US10401234
申请日：2003-03-27
IPC分类号： G06F12/00
CPC分类号： G06F12/145 , G06F12/1458
摘要： The disclosed embodiments may relate to memory window access, which may include a memory window and protection domain associated with a process. The memory window access setting or bit may also allow a plurality of memory windows to be associated with a protection domain for a process. The memory window access setting or bit may allow access to the memory window to be for the queue pairs in a certain protection domain or a designated queue pair.
摘要翻译： 所公开的实施例可以涉及存储器窗口访问，其可以包括与进程相关联的存储器窗口和保护域。 存储器窗口访问设置或位还可以允许多个存储器窗口与进程的保护域相关联。 存储器窗口访问设置或位可以允许访问存储器窗口以用于特定保护域或指定队列对中的队列对。
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