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39 条记录 (耗时 0.03 秒)

    Method and system of copying a memory area between processor elements for lock-step execution
    6.
    发明授权
    Method and system of copying a memory area between processor elements for lock-step execution 有权
    在处理器元件之间复制存储区域以进行锁步执行的方法和系统

    公开(公告)号：US07933966B2

    公开(公告)日：2011-04-26

    申请号：US11114318

    申请日：2005-04-26

    申请人： Thomas J. Kondo ,  Robert L. Jardine ,  James S. Klecka ,  William F. Bruckert ,  David J. Garcia ,  James R. Smullen ,  Patrick H. Barnes

    发明人： Thomas J. Kondo ,  Robert L. Jardine ,  James S. Klecka ,  William F. Bruckert ,  David J. Garcia ,  James R. Smullen ,  Patrick H. Barnes

    IPC分类号： G06F15/167

    CPC分类号： G06F11/1658 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/185

    摘要： A method and system of copying a memory area between processor elements for lock-step execution. At least some of the illustrative embodiments may be a method comprising executing duplicate copies of a first program in a first processor of a first multiprocessor computer system and in a first processor of a second multiprocessor computer system (the executing substantially in lock-step), executing a second program in a second processor element of the first multiprocessor computer system (the first and second processors of the first multiprocessor computer system sharing an input/output (I/O) bridge), copying a memory area of the second program executing in the second processor element of the first multiprocessor computer system to a memory of a second processor element in the second multiprocessor computer system while the duplicate copies of the first program are executing in the first processor elements, and then executing duplicate copies of the second program in the second processors in lock-step.

    摘要翻译： 在处理器元件之间复制存储区域以进行锁步执行的方法和系统。 示例性实施例中的至少一些可以是包括在第一多处理器计算机系统的第一处理器和第二多处理器计算机系统的第一处理器中执行第一程序的重复副本（执行基本上是锁定步骤）的方法， 在第一多处理器计算机系统的第二处理器元件（共享输入/输出（I / O）桥的第一多处理器计算机系统的第一和第二处理器）中执行第二程序，复制第二程序中执行的第二程序的存储区域 所述第一多处理器计算机系统的第二处理器元件到所述第二多处理器计算机系统中的第二处理器元件的存储器，同时所述第一程序的副本在所述第一处理器元件中执行，然后执行所述第二程序的副本 第二个处理器在锁步。

    System and method for implementing error detection and recovery in a system area network
    8.
    发明授权
    System and method for implementing error detection and recovery in a system area network 有权
    在系统区域网络中实现错误检测和恢复的系统和方法

    公开(公告)号：US06545981B1

    公开(公告)日：2003-04-08

    申请号：US09224115

    申请日：1998-12-30

    申请人： David J. Garcia ,  Richard O. Larson ,  Stephen G. Low ,  William J. Watson

    发明人： David J. Garcia ,  Richard O. Larson ,  Stephen G. Low ,  William J. Watson

    IPC分类号： H04L1256

    CPC分类号： H04L29/06 ,  G06F12/023 ,  G06F12/0292 ,  G06F12/1081 ,  H04L1/16 ,  H04L1/188 ,  H04L1/22 ,  H04L49/25 ,  H04L49/351 ,  H04L49/555 ,  H04L49/90 ,  H04L69/26 ,  H04L69/326

    摘要： A system and method for facilitating both in-order and out-of-order packet reception in a SAN includes requestor and responder nodes, coupled by a plurality of paths, that maintain the good and bad status of each path and also maintain local copies of a message sequence number. If an error occurs for a transaction over a given path, the requestor informs the responder, over a good path, that the given path has failed and both nodes update their path status to indicate that the given path is bad. A barrier transaction is used by the requestor to determine whether the error is transient or permanent, and, if the error is transient, the requestor retries the transaction.

    摘要翻译： 一种用于促进SAN中有序和无序分组接收的系统和方法包括通过多个路径耦合的请求者和响应者节点，其保持每个路径的良好和不良状态，并且还保持 一个消息序列号。 如果给定路径上的事务发生错误，则请求者通过良好的路径通知响应者给定路径失败，并且两个节点都更新其路径状态，以指示给定的路径不正确。 请求者使用屏障事务来确定错误是暂时的还是永久的，如果错误是短暂的，请求者重试事务。

    System and method for implementing multi-pathing data transfers in a system area network
    9.
    发明授权
    System and method for implementing multi-pathing data transfers in a system area network 有权
    在系统区域网络中实现多路径数据传输的系统和方法

    公开(公告)号：US06493343B1

    公开(公告)日：2002-12-10

    申请号：US09224114

    申请日：1998-12-30

    申请人： David J. Garcia ,  Richard O. Larson

    发明人： David J. Garcia ,  Richard O. Larson

    IPC分类号： H04L1228

    CPC分类号： H04L49/30 ,  G06F12/023 ,  G06F12/0292 ,  G06F12/1081 ,  H04L1/16 ,  H04L1/188 ,  H04L1/22 ,  H04L29/06 ,  H04L49/557 ,  H04L49/90 ,  H04L69/26 ,  H04L69/324 ,  H04L69/326

    摘要： A system and method for facilitating both in-order and out-of-order packet reception in a SAN includes requester and responder nodes that maintain local copies of a message sequence number. Each request packet includes an ordering field specifying whether the packets must be received in-order. The request node includes a copy of the local sequence number in each packet transmitted and increments its local copy of the sequence number only for packets that must be received in order. The responder node includes the received message sequence number in all response packets and increments its local copy of the message sequence number only if the ordering field specifies that the packets must be received in order.

    摘要翻译： 一种用于促进SAN中的顺序和无序分组接收的系统和方法包括维护消息序列号的本地副本的请求者和响应者节点。 每个请求分组包括一个排序字段，指定分组是否必须按顺序接收。 请求节点包括发送的每个分组中的本地序列号的副本，并且仅对于必须按顺序接收的分组递增其序列号的本地副本。 响应者节点在所有响应分组中包括接收到的消息序列号，并且只有当排序字段指定必须按顺序接收分组时，才增加其消息序列号的本地副本。

    Method and system of exchanging information between processors
    10.
    发明授权
    Method and system of exchanging information between processors 有权
    处理器之间交换信息的方法和系统

    公开(公告)号：US08799706B2

    公开(公告)日：2014-08-05

    申请号：US11042985

    申请日：2005-01-25

    申请人： William F. Bruckert ,  David J. Garcia ,  Thomas A. Heynemann ,  James S. Klecka ,  Jeffrey A. Sprouse

    发明人： William F. Bruckert ,  David J. Garcia ,  Thomas A. Heynemann ,  James S. Klecka ,  Jeffrey A. Sprouse

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1687 ,  G06F11/1645

    摘要： A method and system of exchanging information between processors. At least some of the illustrative embodiments may be a method comprising exchanging information between a plurality of processors by writing (by a first processor) a first datum to a logic device and then continuing processing of a user program by the first processor, writing (by a second processor) a second datum to the logic device and then continuing processing of a user program by the second processor, and writing (by the logic device) the first and second datum to each of the first and second processors after all the processors have written their respective datum to the logic device.

    摘要翻译： 一种在处理器之间交换信息的方法和系统。 说明性实施例中的至少一些可以是一种方法，包括通过将（第一处理器）第一数据写入逻辑设备，然后由第一处理器继续处理用户程序，在多个处理器之间交换信息，由（第 第二处理器）到逻辑设备的第二数据，然后由第二处理器继续处理用户程序，并且在所有处理器具有第一处理器和第二处理器之后，通过逻辑器件将第一和第二数据写入第一和第二处理器 将其各自的基准写入逻辑设备。