公开(公告)号：US07436702B2

公开(公告)日：2008-10-14

申请号：US11469351

申请日：2006-08-31

申请人： David Naura ,  Christophe Moreaux ,  Ahmed Kari ,  Pierre Rizzo

发明人： David Naura ,  Christophe Moreaux ,  Ahmed Kari ,  Pierre Rizzo

IPC分类号： G11C11/34

CPC分类号： G11C16/22

摘要： A method protects against a global data erasure an integrated circuit comprising an electrically programmable data memory and a control unit to execute commands for reading or writing in the memory. The method includes the steps of providing, in the integrated circuit, electrically programmable reference memory cells, at putting the integrated circuit into service, storing, in the reference memory cells, bits of determined value forming an authorized combination of bits and, during the operation of the integrated circuit following its putting into service, reading and evaluating the reference memory cells and blocking the integrated circuit if the reference memory cells contain a forbidden combination of bits different from the authorized combination.

摘要翻译： 一种防止全局数据擦除的集成电路的方法，该集成电路包括电可编程数据存储器和控制单元，以执行用于读取或写入存储器的命令。 该方法包括以下步骤：在集成电路中提供电可编程参考存储器单元，在将集成电路投入使用时，在参考存储器单元中存储形成授权的位组合的确定值的位，并且在操作期间 如果参考存储器单元包含与授权组合不同的位的禁止组合，则集成电路在其投入使用之后，读取和评估参考存储器单元并阻塞集成电路。

公开(公告)号：US20070153581A1

公开(公告)日：2007-07-05

申请号：US11610628

申请日：2006-12-14

申请人： Ahmed Kari ,  Christophe Moreaux ,  David Naura ,  Pierre Rizzo

发明人： Ahmed Kari ,  Christophe Moreaux ,  David Naura ,  Pierre Rizzo

IPC分类号： G11C11/34

CPC分类号： G11C16/349

摘要： A method for executing a write command for writing a binary word in a programmable memory, comprises writing each of the bits in a programmed state of a binary word to be written in a corresponding memory cell of the memory, reading each bit of the word written in the memory corresponding to a bit in the programmed state of the word to be written, comparing each bit in the programmed state of the word to be written with a corresponding bit read in the memory, and generating an error signal if at least one bit of the word to be written in the programmed state is different from the corresponding bit read. Application of the method can be particularly but not exclusively to integrated circuits for chip cards.

摘要翻译： 一种用于执行用于在可编程存储器中写入二进制字的写入命令的方法，包括将要写入存储器的相应存储器单元的二进制字的编程状态中的每一位写入，读取写入的字的每个位 在对应于要写入的字的编程状态中的位的存储器中，将要写入的字的编程状态中的每个比特与在存储器中读取的相应位进行比较，并且如果至少一个位 要写入编程状态的字与相应的位读取不同。 该方法的应用可以特别地但不排他地用于芯片卡的集成电路。

公开(公告)号：US07237157B2

公开(公告)日：2007-06-26

申请号：US10844978

申请日：2004-05-13

申请人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

发明人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

IPC分类号： G11C29/08 ,  G11C29/06

CPC分类号： G11C29/46

摘要： A procedure is provided for identifying an operating mode of a device, such as an EEPROM memory that communicates according to a communication protocol, such as “I2C” (Inter Integrated Circuit). The signal is an “ACK” or “ACKNOWLEDGE” signal. At least one operating mode of a device is identified by a time lag from the time the signal (ACK) is transmitted relative to the time foreseen by the protocol for the signal. This approach can be used to verify that the test mode commands (read or write) have been taken into account correctly.

摘要翻译： 提供了用于识别诸如“I 2 C”（集成内部电路）等通信协议进行通信的EEPROM存储器的装置的操作模式的过程。 信号是“ACK”或“ACKNOWLEDGE”信号。 从信号（ACK）相对于信号协议所预见的时间发送的时间，通过时间滞后来识别设备的至少一个操作模式。 该方法可用于验证测试模式命令（读取或写入）是否被正确地考虑在内。

公开(公告)号：US20070053233A1

公开(公告)日：2007-03-08

申请号：US11468257

申请日：2006-08-29

申请人： David Naura ,  Christophe Moreaux ,  Ahmed Kari ,  Pierre Rizzo

发明人： David Naura ,  Christophe Moreaux ,  Ahmed Kari ,  Pierre Rizzo

IPC分类号： G11C7/00

CPC分类号： G11C16/344 ,  G11C16/0433

摘要： A method checks the state of a set of memory cells of a memory comprising memory cells arranged in a memory array, means for selecting a memory cell, and a sense amplifier for supplying a state of the selected memory cell depending on whether the selected memory cell is conductive or non-conductive. The method includes features wherein all the memory cells of a set grouping together several memory cells are selected, and then simultaneously coupled to the sense amplifier, and the sense amplifier supplies a global state of all the selected memory cells to which it is coupled, if the latter are simultaneously non-conductive. Application is provided to the checking of a command for block-erasing a memory.

摘要翻译： 一种方法检查包括存储器阵列中布置的存储单元的存储器组的集合的状态，用于选择存储单元的装置以及用于根据所选存储单元是否提供所选存储单元的状态的读出放大器 是导电或不导电的。 该方法包括其中选择分组在一起的几个存储器单元的集合的所有存储单元，然后同时耦合到读出放大器的特征，并且读出放大器提供与其耦合到的所有选定存储单元的全局状态，如果 后者同时不导电。 提供了用于检查用于块擦除存储器的命令的应用。

公开(公告)号：US06714450B2

公开(公告)日：2004-03-30

申请号：US10100511

申请日：2002-03-18

申请人： Bertrand Bertrand ,  Mohamad Chehadi ,  David Naura

发明人： Bertrand Bertrand ,  Mohamad Chehadi ,  David Naura

IPC分类号： G11C1608

CPC分类号： G11C16/12 ,  G11C16/0433

摘要： An electrically programmable and erasable memory includes memory cells connected to word lines and to bit lines arranged in columns. Bit lines selection transistors are driven by bit lines selection signals. Column selection latches each includes a locking element for a column selection signal and a circuit for delivering a gate control signal which depends on the output of the locking element. Each column selection latch delivers, in addition to a gate control signal, a bit lines selection signal. This signal depends on the output of the locking element at least during programming and reading phases of the memory cells.

摘要翻译： 电可编程和可擦除存储器包括连接到字线和排列成列的位线的存储器单元。 位线选择晶体管由位线选择信号驱动。 列选择锁存器各自包括用于列选择信号的锁定元件和用于传送取决于锁定元件的输出的门控制信号的电路。 每个列选择锁存器除了门控制信号之外还提供位线选择信号。 该信号至少在存储器单元的编程和读取阶段期间取决于锁定元件的输出。

公开(公告)号：US06504791B1

公开(公告)日：2003-01-07

申请号：US09660303

申请日：2000-09-12

申请人： David Naura ,  Sebastien Zink ,  Bertrand Bertrand

发明人： David Naura ,  Sebastien Zink ,  Bertrand Bertrand

IPC分类号： G11C800

CPC分类号： G11C16/10

摘要： A method of writing in page mode in an electrically erasable and programmable non-volatile memory includes an initialization phase of writing an information element for the selection of the page in a storage latch associated with a column of the non-volatile memory array, and the writing in a temporary memory of each of the data bits to be written in the page. A write phase includes the selection of rows of the non-volatile memory array according to the contents of the temporary memory. A page mode write circuit includes one latch per column of the non-volatile memory array to contain a page selection information element, and a control logic circuit to give the row selection signals as a function of the contents of the temporary memory in a phase for writing the column of the non-volatile memory array.

摘要翻译： 在电可擦除可编程非易失性存储器中以页模式写入的方法包括：在与非易失性存储器阵列的列相关联的存储锁存器中写入用于页的选择的信息元素的初始化阶段，以及 在临时存储器中写入要写入页面的每个数据位。 写入阶段包括根据临时存储器的内容来选择非易失性存储器阵列的行。 页面模式写入电路包括每列非易失性存储器阵列中的一个锁存器以包含页面选择信息元素，以及控制逻辑电路，用于以相位为单位给出作为临时存储器的内容的函数的行选择信号 写入非易失性存储器阵列的列。

公开(公告)号：US06324117B1

公开(公告)日：2001-11-27

申请号：US09676434

申请日：2000-09-29

申请人： Sébastien Zink ,  Bertrand Bertrand ,  David Naura

发明人： Sébastien Zink ,  Bertrand Bertrand ,  David Naura

IPC分类号： G11C800

CPC分类号： G11C5/066 ,  G11C8/10 ,  G11C2216/30

摘要： The invention proposes a method of selecting a determined access line of a serial access type integrated circuit memory, a determined access line being selectable among a determined group of access lines (AL0-AL7) of the same nature, for example a group of bit lines or a group of word lines, a line code on p bits being respectively associated to each access line of the group, which consists in pre-activating all the access lines of the group, then ofdeactivating progressively the other access lines as a function of the bits (Ai) of the line code of the access line to select received in series via the serial data input of the memory such that, in the end, only the access line to be selected remains activated.

摘要翻译： 本发明提出了一种选择串行接入型集成电路存储器的确定的接入线路的方法，所确定的接入线路可在相同性质的确定的接入线路组（AL0-AL7）之间选择，例如一组位线 或一组字线，p位上的行代码分别与组的每个访问行相关联，其中包括预先激活该组的所有访问行，然后逐渐地将其他访问行的活动作为 通过存储器的串行数据输入串行接收的接入线的线路码的位（Ai），使得最终只有要被选择的接入线保持激活。

公开(公告)号：US6125063A

公开(公告)日：2000-09-26

申请号：US154268

申请日：1998-09-16

申请人： Mohamad Chehadi ,  David Naura

发明人： Mohamad Chehadi ,  David Naura

IPC分类号： G11C16/30 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C29/50 ,  G11C16/04

摘要： In a memory integrated circuit comprising an internal circuit for the generation of a programming high voltage and comprising a first pad designed to receive a main logic supply voltage below five volts, a second specific supply pad is designed to supply the high voltage generation circuit. This enables the application of a specific logic supply voltage with a voltage level greater than that of the main logic supply voltage in test mode or in application mode.

摘要翻译： 在包括用于产生编程高电压的内部电路并包括被设计为接收低于五伏的主逻辑电源电压的第一焊盘的存储器集成电路中，第二特定供电焊盘被设计成供应高压发生电路。 这样可以在测试模式或应用模式下，施加电压值大于主逻辑电源电压的特定逻辑电源电压。

公开(公告)号：US08180992B2

公开(公告)日：2012-05-15

申请号：US12036667

申请日：2008-02-25

申请人： Christophe Moreaux ,  Ahmed Kari ,  David Naura ,  Pierre Rizzo

发明人： Christophe Moreaux ,  Ahmed Kari ,  David Naura ,  Pierre Rizzo

IPC分类号： G06F12/06

CPC分类号： G06F12/0292

摘要： A method for configuring a memory space, the method including reading a piece of configuration information in the memory space, determining a division of at least one part of the memory space into memory banks according to the configuration information read; and allocating to each of the memory banks an access number to be used to access a data location in the memory bank, in combination with a logic address of the location in the memory bank.

摘要翻译： 一种用于配置存储器空间的方法，所述方法包括：在所述存储器空间中读取一条配置信息，根据读取的配置信息确定所述存储器空间的至少一部分划分为存储体; 以及与所述存储体中的所述位置的逻辑地址组合，分配给所述存储体中用于访问所述存储体中的数据位置的访问号码。

公开(公告)号：US07679945B2

公开(公告)日：2010-03-16

申请号：US12043766

申请日：2008-03-06

申请人： Pierre Rizzo ,  Christophe Moreaux ,  David Naura ,  Ahmed Kari

发明人： Pierre Rizzo ,  Christophe Moreaux ,  David Naura ,  Ahmed Kari

IPC分类号： G11C11/24

CPC分类号： G11C11/4023 ,  G06K7/10029 ,  G06K7/10059 ,  G06K19/07749

摘要： A persistent volatile memory cell memorizes a binary datum during a retention time independent from a supply voltage of the memory cell. The memory cell comprises a capacitive memory point supplying a persistent voltage and having a determined discharge time, a switch for triggering the discharge of the memory point when an erase signal has an active value, a switch for triggering the charge of the memory point when a write signal has an active value, and a sense-amplifier circuit having an input receiving the persistent voltage, and an output supplying the binary datum. The memory cell can be applied to the management of an inventory flag in a contactless integrated circuit.

摘要翻译： 永久性易失性存储器单元在独立于存储器单元的电源电压的保持时间期间存储二进制数据。 存储单元包括提供持续电压并具有确定的放电时间的电容性存储器点，当擦除信号具有有效值时用于触发存储点放电的开关，当触发存储点的充电时，当a 写信号具有有效值，以及具有接收持续电压的输入的读出放大器电路和提供二进制数据的输出。 存储单元可应用于无接触集成电路中的库存标志的管理。