公开(公告)号：US07012837B2

公开(公告)日：2006-03-14

申请号：US10903927

申请日：2004-07-31

申请人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

发明人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C8/08 ,  G11C16/14

摘要： A method is provided for erasing or programming at least one memory cell of a non-volatile memory. According to the method, a state fixation pulse is applied to a floating gate transistor of the memory cell. The state fixation pulse also includes, successively, a portion at a reference voltage, and a state fixation portion at a voltage with sufficient amplitude for the transfer of electrons between the drain and the gate of the floating gate transistor. Additionally, an external adjustment signal is applied to the memory to adjust the state fixation portion to a predetermined duration, and the state fixation portion is adjusted to the predetermined duration in real time as a function of the state of the adjustment signal. Also provided is a non-volatile memory.

摘要翻译： 提供一种用于擦除或编程非易失性存储器的至少一个存储单元的方法。 根据该方法，将状态固定脉冲施加到存储单元的浮栅晶体管。 状态固定脉冲还连续地包括参考电压的一部分，以及具有足够幅度的电压的状态固定部分，用于在浮置栅晶体管的漏极和栅极之间传输电子。 此外，外部调整信号被施加到存储器以将状态固定部分调整到预定的持续时间，并且根据调整信号的状态将状态固定部分实时地调整到预定的持续时间。 还提供了非易失性存储器。

公开(公告)号：US06621737B2

公开(公告)日：2003-09-16

申请号：US10096531

申请日：2002-03-11

申请人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

发明人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

IPC分类号： G11C1606

CPC分类号： G11C16/12

摘要： A circuit produces a voltage for the erasure or programming of a memory cell. The circuit includes a capacitor, and a discharge circuit connected to a first terminal of the capacitor. The discharge circuit includes a first transistor, a drain of which is connected to the first terminal of the capacitor. The first transistor activates the discharge circuit when a discharge signal is received by a gate of the first transistor. The discharge circuit includes a slow discharge arm and a fast discharge arm parallel-connected to the source of the first transistor. The discharge circuit produces a low discharge current or a high discharge current for discharging the capacitor as a function of an operating mode selection signal.

公开(公告)号：US07237157B2

公开(公告)日：2007-06-26

申请号：US10844978

申请日：2004-05-13

申请人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

发明人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

IPC分类号： G11C29/08 ,  G11C29/06

CPC分类号： G11C29/46

摘要： A procedure is provided for identifying an operating mode of a device, such as an EEPROM memory that communicates according to a communication protocol, such as “I2C” (Inter Integrated Circuit). The signal is an “ACK” or “ACKNOWLEDGE” signal. At least one operating mode of a device is identified by a time lag from the time the signal (ACK) is transmitted relative to the time foreseen by the protocol for the signal. This approach can be used to verify that the test mode commands (read or write) have been taken into account correctly.

摘要翻译： 提供了用于识别诸如“I 2 C”（集成内部电路）等通信协议进行通信的EEPROM存储器的装置的操作模式的过程。 信号是“ACK”或“ACKNOWLEDGE”信号。 从信号（ACK）相对于信号协议所预见的时间发送的时间，通过时间滞后来识别设备的至少一个操作模式。 该方法可用于验证测试模式命令（读取或写入）是否被正确地考虑在内。

公开(公告)号：US06714450B2

公开(公告)日：2004-03-30

申请号：US10100511

申请日：2002-03-18

申请人： Bertrand Bertrand ,  Mohamad Chehadi ,  David Naura

发明人： Bertrand Bertrand ,  Mohamad Chehadi ,  David Naura

IPC分类号： G11C1608

CPC分类号： G11C16/12 ,  G11C16/0433

摘要： An electrically programmable and erasable memory includes memory cells connected to word lines and to bit lines arranged in columns. Bit lines selection transistors are driven by bit lines selection signals. Column selection latches each includes a locking element for a column selection signal and a circuit for delivering a gate control signal which depends on the output of the locking element. Each column selection latch delivers, in addition to a gate control signal, a bit lines selection signal. This signal depends on the output of the locking element at least during programming and reading phases of the memory cells.

摘要翻译： 电可编程和可擦除存储器包括连接到字线和排列成列的位线的存储器单元。 位线选择晶体管由位线选择信号驱动。 列选择锁存器各自包括用于列选择信号的锁定元件和用于传送取决于锁定元件的输出的门控制信号的电路。 每个列选择锁存器除了门控制信号之外还提供位线选择信号。 该信号至少在存储器单元的编程和读取阶段期间取决于锁定元件的输出。

公开(公告)号：US6125063A

公开(公告)日：2000-09-26

申请号：US154268

申请日：1998-09-16

申请人： Mohamad Chehadi ,  David Naura

发明人： Mohamad Chehadi ,  David Naura

IPC分类号： G11C16/30 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C16/30 ,  G11C29/50 ,  G11C16/04

摘要： In a memory integrated circuit comprising an internal circuit for the generation of a programming high voltage and comprising a first pad designed to receive a main logic supply voltage below five volts, a second specific supply pad is designed to supply the high voltage generation circuit. This enables the application of a specific logic supply voltage with a voltage level greater than that of the main logic supply voltage in test mode or in application mode.

摘要翻译： 在包括用于产生编程高电压的内部电路并包括被设计为接收低于五伏的主逻辑电源电压的第一焊盘的存储器集成电路中，第二特定供电焊盘被设计成供应高压发生电路。 这样可以在测试模式或应用模式下，施加电压值大于主逻辑电源电压的特定逻辑电源电压。

公开(公告)号：US20050207230A1

公开(公告)日：2005-09-22

申请号：US10903927

申请日：2004-07-31

申请人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

发明人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

IPC分类号： G11C8/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/04 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C8/08 ,  G11C16/14

摘要： A method is provided for erasing or programming at least one memory cell of a non-volatile memory. According to the method, a state fixation pulse is applied to a floating gate transistor of the memory cell. The state fixation pulse also includes, successively, a portion at a reference voltage, and a state fixation portion at a voltage with sufficient amplitude for the transfer of electrons between the drain and the gate of the floating gate transistor. Additionally, an external adjustment signal is applied to the memory to adjust the state fixation portion to a predetermined duration, and the state fixation portion is adjusted to the predetermined duration in real time as a function of the state of the adjustment signal. Also provided is a non-volatile memory.

摘要翻译： 提供一种用于擦除或编程非易失性存储器的至少一个存储单元的方法。 根据该方法，将状态固定脉冲施加到存储单元的浮栅晶体管。 状态固定脉冲还连续地包括参考电压的一部分，以及具有足够幅度的电压的状态固定部分，用于在浮置栅晶体管的漏极和栅极之间传输电子。 此外，外部调整信号被施加到存储器以将状态固定部分调整到预定的持续时间，并且根据调整信号的状态将状态固定部分实时地调整到预定的持续时间。 还提供了非易失性存储器。

公开(公告)号：US20050015533A1

公开(公告)日：2005-01-20

申请号：US10844978

申请日：2004-05-13

申请人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

发明人： David Naura ,  Bertrand Bertrand ,  Mohamad Chehadi

IPC分类号： G06F11/00 ,  G06F13/42 ,  G07C3/00 ,  G11C29/00 ,  G11C29/46

CPC分类号： G11C29/46

摘要： A procedure is provided for identifying an operating mode of a device, such as an EEPROM memory that communicates according to a communication protocol, such as “I2C” (Inter Integrated Circuit). The signal is an “ACK” or “ACKNOWLEDGE” signal. At least one operating mode of a device is identified by a time lag from the time the signal (ACK) is transmitted relative to the time foreseen by the protocol for the signal. This approach can be used to verify that the test mode commands (read or write) have been taken into account correctly.

摘要翻译： 提供了用于识别诸如“I2C”（集成内部电路）等通信协议进行通信的EEPROM存储器的设备的操作模式的过程。 信号是“ACK”或“ACKNOWLEDGE”信号。 从信号（ACK）相对于信号协议所预见的时间发送的时间，通过时间滞后来识别设备的至少一个操作模式。 该方法可用于验证测试模式命令（读取或写入）是否被正确地考虑在内。

公开(公告)号：US06538931B1

公开(公告)日：2003-03-25

申请号：US09594243

申请日：2000-06-15

申请人： Mohamad Chehadi ,  David Naura

发明人： Mohamad Chehadi ,  David Naura

IPC分类号： G11C700

CPC分类号： G11C16/30 ,  G11C16/04 ,  G11C29/50

摘要： In a memory integrated circuit comprising an internal circuit for the generation of a programming high voltage and comprising a first pad designed to receive a main logic supply voltage below five volts, a second specific supply pad is designed to supply the high voltage generation circuit. This enables the by application of a specific logic supply voltage with a voltage level greater than that of the main logic supply voltage in test mode or in application mode.

摘要翻译： 在包括用于产生编程高电压的内部电路并包括被设计为接收低于五伏的主逻辑电源电压的第一焊盘的存储器集成电路中，第二特定供电焊盘被设计成供应高压发生电路。 这样可以在测试模式或应用模式下，施加电压值大于主逻辑电源电压的特定逻辑电源电压。

公开(公告)号：US06621720B1

公开(公告)日：2003-09-16

申请号：US10019771

申请日：2001-12-27

申请人： Jean Devin ,  Mohamad Chehadi

发明人： Jean Devin ,  Mohamad Chehadi

IPC分类号： H02M318

CPC分类号： G11C16/12 ,  G11C16/30

摘要： The integrated circuit includes a detection circuit and a rectifier circuit that are series-connected, to provide a rectified voltage, and a low voltage regulation circuit that receives the rectified voltage and provides a low voltage. According to the invention, the circuit also has a voltage production circuit that receives the rectified voltage and produces a high voltage different from the low voltage. In one embodiment, the circuit also includes a memory having a memory array receiving the low voltage and the high voltage.

摘要翻译： 集成电路包括串联连接的提供整流电压的检测电路和整流电路，以及接收整流电压并提供低电压的低压调节电路。 根据本发明，电路还具有接收整流电压并产生不同于低电压的高电压的电压产生电路。 在一个实施例中，电路还包括具有接收低电压和高电压的存储器阵列的存储器。

公开(公告)号：US6034889A

公开(公告)日：2000-03-07

申请号：US177899

申请日：1998-10-23

申请人： Christophe Mani ,  Mohamad Chehadi

发明人： Christophe Mani ,  Mohamad Chehadi

IPC分类号： G06F1/00 ,  G06F12/14 ,  G06F21/00 ,  G11C8/20 ,  G11C16/22 ,  G11C7/00

CPC分类号： G06F21/79 ,  G06F12/1441 ,  G11C16/22 ,  G11C8/20

摘要： An electrically erasable and programmable non-volatile semiconductor memory includes memory registers that are addressable individually or by blocks. The memory also has a protection register in which a protection word can be written. The protection word has a given number of bits that encode a boundary address of the memory register or a block of memory registers. The boundary address divides the memory space into an upper zone and a lower zone. The protection word also has a zone bit whose value determines which of the two zones of the memory is to be write protectable.

摘要翻译： 电可擦除和可编程的非易失性半导体存储器包括可单独地或通过块寻址的存储器寄存器。 存储器还具有可以写保护字的保护寄存器。 保护字具有编码存储器寄存器的边界地址或存储器寄存器块的给定位数。 边界地址将内存空间划分为上区和下区。 保护字还具有一个区段位，其值决定了存储器的两个区域中哪一个是可写保护的。