公开(公告)号：US4728818A

公开(公告)日：1988-03-01

申请号：US942669

申请日：1986-12-17

Applicant: David P. Chengson ,  Aurangzeb K. Khan

Inventor： David P. Chengson ,  Aurangzeb K. Khan

IPC: H03K3/286 ,  H03K3/2885 ,  H03K19/086 ,  H03K3/284 ,  H03K3/29

CPC classification number: H03K3/2885 ,  H03K19/0863

Abstract: An improved EFL gate which provides concurrent true and complementary outputs. An input transistor has its base coupled to an input and its emitter coupled to an emitter of a reference transistor. The reference transistor has its base coupled to a voltage reference and its collector coupled to the base of a true output transistor. The emitter of the true output transistor provides the true output, while its collector is coupled to a voltage supply. A complementary output transistor has its base coupled to the collector of the input transistor with its emitter providing the complementary output. Its collector is coupled to the voltage supply, as is the collector of the input transistor.

公开(公告)号：US09237003B1

公开(公告)日：2016-01-12

申请号：US13204391

申请日：2011-08-05

Applicant: David P. Chengson ,  Chang-Hong Wu

Inventor： David P. Chengson ,  Chang-Hong Wu

IPC: H04L7/033

CPC classification number: H04L7/033 ,  H04L25/49

Abstract: In general, techniques are described that insert one or more bits into a digital bit stream to maintain an overall transition density in the digital bit stream. Maintaining the overall transition density facilitates the generation of a recovered clock by a phase-locked loop (PLL) circuit of a receiver. For example, when a data transition ratio for a portion of the digital bit stream is less than a desired data transition ratio, the techniques insert additional bits to increase the overall transition density of the digital bit stream.

Abstract translation: 通常，描述了将一个或多个比特插入到数字比特流中以保持数字比特流中的总体转移密度的技术。 维持整个转换密度有助于通过接收机的锁相环（PLL）电路产生恢复的时钟。 例如，当数字比特流的一部分的数据转换比小于期望的数据转换比时，该技术插入附加比特以增加数字比特流的整体转换密度。

公开(公告)号：US08411695B1

公开(公告)日：2013-04-02

申请号：US11134256

申请日：2005-05-23

Applicant: David P. Chengson ,  Jaya Bandyopadhyay

Inventor： David P. Chengson ,  Jaya Bandyopadhyay

IPC: H04L12/28

CPC classification number: H04J3/06 ,  G06F13/4022 ,  H04J3/0697 ,  H04L7/0008

Abstract: A multi-interface bus allows for different bus standards to be implemented over the same set of physical bus lines. More particularly, in one implementation, the system includes a first circuit board, a second circuit board, and a bus connecting the first and second circuit boards. The second circuit board is configured to communicate with the first circuit board using either a synchronous or an asynchronous bus protocol determined based on a bus protocol used by the first circuit board.

Abstract translation: 多接口总线允许在同一组物理总线上实现不同的总线标准。 更具体地，在一个实施方式中，该系统包括第一电路板，第二电路板和连接第一和第二电路板的总线。 第二电路板被配置为使用基于由第一电路板使用的总线协议确定的同步或异步总线协议与第一电路板通信。

公开(公告)号：US20110161544A1

公开(公告)日：2011-06-30

申请号：US12648373

申请日：2009-12-29

Applicant: David P. Chengson ,  Chang-Hong Wu

Inventor： David P. Chengson ,  Chang-Hong Wu

IPC: G06F13/14 ,  G06F13/00 ,  G06F1/04

CPC classification number: G06F13/1689 ,  H04L25/03866 ,  H04L25/06

Abstract: A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams.

Abstract translation: 一个设备跨设备的第一个组件和第二个组件应用同步时钟，并从一组串行链路指定一个特定的串行链路作为主串行链路。 该设备还将剩余的串行链路指定为从串行链路，通过主串行链路提供编码数据流，并通过从串行链路提供未编码和加扰的数据流。

公开(公告)号：US5041747A

公开(公告)日：1991-08-20

申请号：US889439

申请日：1986-07-23

Applicant: David P. Chengson ,  H. William Wang

Inventor： David P. Chengson ,  H. William Wang

IPC: G05F1/46 ,  H03K19/003 ,  H03K19/086

CPC classification number: H03K19/086 ,  G05F1/466 ,  H03K19/00323

Abstract: An integrated circuit chip carries a number of electronic circuits, at least one of which includes, in its output stage, a control device that responds to a reference signal to adjust the output current-handling capability of the electronic circuit, thereby regulating the signal propagation delay exhibited by the electronic circuit. The reference circuit is generated by a digital-to-analog circuit that is also formed on the chip. The digital-to-analog circuit is coupled to a number of contact elements disposed on an outer surface of the package containing the integrated circuit chip that can be selectively interconnected to a DC voltage to choose the value of the reference signal.

Abstract translation: 集成电路芯片承载多个电子电路，其中至少一个在其输出级中包括响应参考信号以调整电子电路的输出电流处理能力的控制装置，从而调节信号传播 延迟由电子电路表现出来。 参考电路由也在芯片上形成的数模转换电路产生。 数模转换电路耦合到多个接触元件，该接触元件设置在包含集成电路芯片的封装的外表面上，该集成电路芯片可选择性地互连到直流电压以选择参考信号的值。