公开(公告)号：US09244798B1

公开(公告)日：2016-01-26

申请号：US13164533

申请日：2011-06-20

Applicant: Kaushik Kuila ,  David T. Hass

Inventor： Kaushik Kuila ,  David T. Hass

IPC: G06F3/00 ,  G06F11/30 ,  G06F3/038

CPC classification number: G06F11/3013 ,  G06F3/038 ,  G06F2221/2121 ,  H04L69/22

Abstract: Disclosed is an approach for implementing a flexible parser for a networking system. A micro-core parser is implemented to process packets in a networking system. The micro-cores of the parser read the packet headers, and perform any suitably programmed tasks upon those packets and packet headers. One or more caches may be associated with the micro-cores to hold the packet headers. A dependency list is used to maintain proper ordering of packets being processed by the micro-cores.

Abstract translation: 公开了一种用于实现网络系统的灵活解析器的方法。 实现了一个微核解析器来处理网络系统中的数据包。 解析器的微核读取数据包头，并在这些数据包和数据包头上执行任何适当编程的任务。 一个或多个高速缓存可以与微核相关联以保持分组报头。 依赖列表用于维护由微核处理的数据包的正确排序。

公开(公告)号：US09088474B2

公开(公告)日：2015-07-21

申请号：US10930937

申请日：2004-08-31

Applicant: Abbas Rashid ,  David T. Hass

Inventor： Abbas Rashid ,  David T. Hass

IPC: H04L12/28 ,  H04L12/931 ,  G06F12/08

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US08953628B2

公开(公告)日：2015-02-10

申请号：US13154413

申请日：2011-06-06

Applicant: David T. Hass

Inventor： David T. Hass

IPC: H04L12/28 ,  H04L12/931 ,  H04J1/16 ,  G06F12/08

CPC classification number: H04L49/00 ,  G06F12/0813 ,  H04L49/30

Abstract: A processor includes a plurality of processor cores, a networking output, and a packet ordering device. The packet ordering device determines an ordering for packets that are processed by the processor cores. The packets are released to the networking output in a determined order.

Abstract translation: 处理器包括多个处理器核心，联网输出和分组排序设备。 分组排序设备确定处理器核心处理的分组的顺序。 数据包以确定的顺序被释放到网络输出。

公开(公告)号：US08037224B2

公开(公告)日：2011-10-11

申请号：US11831887

申请日：2007-07-31

Applicant: Julianne Jiang Zhu ,  David T. Hass

Inventor： Julianne Jiang Zhu ,  David T. Hass

IPC: G06F13/42 ,  G06F13/00 ,  G06F13/14 ,  G06F15/75

CPC classification number: G06F13/4286 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20100318703A1

公开(公告)日：2010-12-16

申请号：US12815092

申请日：2010-06-14

Applicant: Julianne Jiang Zhu ,  David T. Hass

Inventor： Julianne Jiang Zhu ,  David T. Hass

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4286 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20100058101A1

公开(公告)日：2010-03-04

申请号：US12201689

申请日：2008-08-29

Applicant: Ahmed Shahid ,  Kaushik Kuila ,  David T. Hass

Inventor： Ahmed Shahid ,  Kaushik Kuila ,  David T. Hass

IPC: G06F1/00 ,  H04J3/06

CPC classification number: G06F1/00 ,  G06F1/12 ,  G06F1/14 ,  H04J3/0667 ,  H04J3/0685

Abstract: A system and method are provided for reducing a latency associated with timestamps in a multi-core, multi threaded processor. A processor capable of simultaneously processing a plurality of threads is provided. The processor includes a plurality of cores, a plurality of network interfaces for network communication, and a timer circuit for reducing a latency associated with timestamps used for synchronization of the network communication utilizing a precision time protocol.

Abstract translation: 提供了一种用于减少与多核，多线程处理器中的时间戳相关联的等待时间的系统和方法。 提供能够同时处理多个线程的处理器。 处理器包括多个核心，多个用于网络通信的网络接口，以及定时器电路，用于减少与用于使用精确时间协议的网络通信同步的时间戳相关联的等待时间。

公开(公告)号：US20090058693A1

公开(公告)日：2009-03-05

申请号：US11849166

申请日：2007-08-31

Applicant: Robert William Laker ,  David T. Hass

Inventor： Robert William Laker ,  David T. Hass

IPC: H03M7/40

CPC classification number: H03M7/40 ,  H03M7/3086

Abstract: An apparatus to implement Huffman decoding in an INFLATE process in a compression engine. An embodiment of the apparatus includes a bit buffer, a set of comparators, and a lookup table. The bit buffer stores a portion of a compressed data stream. The set of comparators compares the portion of the compressed data stream with a plurality of predetermined values. The lookup table stores a plurality of LZ77 code segments and out puts one of the LZ77 code segments corresponding to an index at least partially derived from a comparison result from the set of comparators.

Abstract translation: 一种用于在压缩引擎中的INFLATE过程中实现霍夫曼解码的装置。 该装置的实施例包括位缓冲器，一组比较器和查找表。 比特缓冲器存储压缩数据流的一部分。 比较器组将压缩数据流的部分与多个预定值进行比较。 查找表存储多个LZ77代码段，并且输出与来自该比较器组的比较结果至少部分地导出的索引相对应的LZ77代码段中的一个。

公开(公告)号：US20080216074A1

公开(公告)日：2008-09-04

申请号：US11961910

申请日：2007-12-20

Applicant: David T. Hass ,  Basab Mukherjee

Inventor： David T. Hass ,  Basab Mukherjee

IPC: G06F9/54 ,  G06F9/46 ,  G06F12/08 ,  G06F12/00

CPC classification number: G06F12/1036 ,  G06F12/0813 ,  H04L49/00

Abstract: An advanced, processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个多线程处理器核心，每个处理器核心具有数据高速缓存和指令高速缓存。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息传递网络耦合到每个处理器核和多个通信端口。 在本发明的实施例的一个方面，数据交换机互连通过其各自的数据高速缓存与每个处理器核心耦合，并且消息传递网络通过其相应的消息站耦合到每个处理器核心。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20080184008A1

公开(公告)日：2008-07-31

申请号：US12019576

申请日：2008-01-24

Applicant: Julianne Jiang Zhu ,  David T. Hass

Inventor： Julianne Jiang Zhu ,  David T. Hass

IPC: G06F15/76 ,  G06F9/02

CPC classification number: G06F13/4286 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3867 ,  G06F12/0813 ,  H04L49/109

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging net work is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract translation: 高级处理器包括多个具有数据高速缓存和指令高速缓存的多线程处理器核心。 数据交换机互连耦合到每个处理器核并被配置为在处理器核之间传递信息。 消息网络工作耦合到每个处理器核和多个通信端口。 数据交换机互连通过其相应的数据高速缓存耦合到每个处理器核心，并且消息传递网络通过其各自的消息站耦合到每个处理器核心。 在本发明的实施例的一个方面，消息传递网络连接到能够支持多个高带宽PCIe通道的高带宽星形拓扑串行总线，例如PCI Express（PCIe）接口。 本发明的优点包括以有效和成本有效的方式在计算机系统和存储器之间提供高带宽通信的能力。

公开(公告)号：US20080140956A1

公开(公告)日：2008-06-12

申请号：US12018144

申请日：2008-01-22

Applicant: David T. Hass ,  Basab Mukherjee

Inventor： David T. Hass ,  Basab Mukherjee

IPC: G06F12/00 ,  G06F12/10

CPC classification number: G06F12/1036 ,  G06F12/0813 ,  H04L49/00

Abstract: An advanced, processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.