公开(公告)号：US06599813B2

公开(公告)日：2003-07-29

申请号：US09895680

申请日：2001-06-29

申请人： Klaus Beyer ,  Dominic Schepis

发明人： Klaus Beyer ,  Dominic Schepis

IPC分类号： H01L2176

CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L29/4908 ,  H01L29/78609

摘要： A method is disclosed for forming shallow trench isolation (STI) on a thin silicon-on-insulator (SOI) substrate. The method comprises depositing a first polysilicon layer; depositing a polish stop layer on the first polysilicon layer; forming a plurality of trenches in the substrate; filling the trenches with silicon oxide; CMP polishing a first portion of the silicon oxide layer down to the polish stop layer; etching a second portion of the silicon oxide layer down to below the polish stop layer and above the first polysilicon layer; removing the polish stop layer; depositing a second polysilicon layer; and forming a polysilicon gate comprised of the first and second polysilicon layers. Well ion implants may be performed prior to gate formation, thereby preventing exposure of STI oxide to sacrificial oxide growth and removal, eliminating excessive recess in STI structures. STI oxide seam leakage due to polysilicon sidewalls remaining after polysilicon gate etch are also avoided.

公开(公告)号：US20120098067A1

公开(公告)日：2012-04-26

申请号：US12908024

申请日：2010-10-20

申请人： Haizhou Yin ,  Dae-Gyu Park ,  Oleg Gluschenkov ,  Zhijiong Luo ,  Dominic Schepis ,  Jun Yuan

发明人： Haizhou Yin ,  Dae-Gyu Park ,  Oleg Gluschenkov ,  Zhijiong Luo ,  Dominic Schepis ,  Jun Yuan

IPC分类号： H01L27/092 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/78

摘要： A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.

摘要翻译： 提供半导体结构。 该结构包括直接在应变硅层的顶部形成的n型场效应晶体管（NFET），以及形成在同一染色硅层顶部的p型场效应晶体管（PFET），但是 通过一层硅 - 锗（SiGe）。 应变硅层可以形成在具有分级Ge含量变化的绝缘材料层或硅 - 锗层的顶部上。 此外，NFET和PFET彼此相邻形成，并且通过形成在应变硅层内部的浅沟槽隔离（STI）分开。 还提供了形成半导体结构的方法。

公开(公告)号：US20080188089A1

公开(公告)日：2008-08-07

申请号：US11671668

申请日：2007-02-06

申请人： Anthony I. Chou ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Shreesh Narasimha ,  Katsunori Onishi ,  Dominic Schepis

发明人： Anthony I. Chou ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Shreesh Narasimha ,  Katsunori Onishi ,  Dominic Schepis

IPC分类号： H01L21/31

CPC分类号： H01L21/32105 ,  H01L21/28035 ,  H01L21/28247

摘要： A method for reducing top notching effects in pre-doped gate structures includes subjecting an etched, pre-doped gate stack structure to a re-oxidation process, the re-oxidation process comprising a radical assisted re-oxidation process so as to result in the formation of an oxide layer over vertical sidewall and horizontal top surfaces of the etched gate stack structure. The resulting oxide layer has a substantially uniform thickness independent of grain boundary orientations of the gate stack structure and independent of the concentration and location of dopant material present therein.

摘要翻译： 用于减少预掺杂栅极结构中的顶部切口效应的方法包括将经蚀刻的预掺杂栅极堆叠结构进行再氧化处理，所述再氧化工艺包括自由基辅助再氧化工艺，以便导致 在蚀刻的栅堆叠结构的垂直侧壁和水平顶表面上形成氧化物层。 所得到的氧化物层具有与栅极堆叠结构的晶界取向无关的基本均匀的厚度，而与其中存在的掺杂剂材料的浓度和位置无关。

公开(公告)号：US20060205189A1

公开(公告)日：2006-09-14

申请号：US11433266

申请日：2006-05-12

申请人： Brian Messenger ,  Renee Mo ,  Dominic Schepis

发明人： Brian Messenger ,  Renee Mo ,  Dominic Schepis

IPC分类号： H01L21/20

CPC分类号： H01L29/66742 ,  H01L29/7842 ,  H01L29/78687

摘要： A manufacturable way to recess silicon that employs an end point detection method for the recess etch and allows tight tolerances on the recess is described for fabricating a strained raised source/drain layer. The method includes forming a monolayer oxygen and carbon on a surface of a doped semiconductor substrate; forming an epi Si layer atop the doped semiconductor substrate; forming at least one gate region on the epi Si layer; selectively etching exposed portions of the epi layer, not protected by the gate region, stopping on and exposing the doped semiconductor substrate using end point detection; and forming a strained SiGe layer on the exposed doped semiconductor substrate. The strained SiGe layer severs as a raised layer in which source/drain diffusion regions can be subsequently formed

摘要翻译： 为了制造应变升高的源极/漏极层，描述了用于凹陷蚀刻采用端点检测方法以及允许在凹槽上的紧密公差的硅的可制造方法。 该方法包括在掺杂半导体衬底的表面上形成单层氧和碳; 在掺杂半导体衬底的顶部形成外延Si层; 在外延Si层上形成至少一个栅极区; 选择性地蚀刻未被栅极区域保护的外延层的暴露部分，使用端点检测停止并暴露掺杂半导体衬底; 以及在所述暴露的掺杂半导体衬底上形成应变SiGe层。 应变SiGe层作为凸起层切断，其中可以随后形成源/漏扩散区

公开(公告)号：US20050040465A1

公开(公告)日：2005-02-24

申请号：US10952286

申请日：2004-09-28

申请人： Heemyong Park ,  Byoung Lee ,  Paul Agnello ,  Dominic Schepis ,  Ghavam Shahidi

发明人： Heemyong Park ,  Byoung Lee ,  Paul Agnello ,  Dominic Schepis ,  Ghavam Shahidi

IPC分类号： H01L21/28 ,  H01L21/00 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/74 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/78612 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41783 ,  H01L29/66772

摘要： A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer; forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and heating the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.

摘要翻译： CMOS器件的方法和结构包括在掩埋氧化物（BOX）衬底上沉积硅绝缘体（SOI）晶片，其中SOI晶片具有预定厚度; 在所述SOI晶片上形成栅电介质; 在所述BOX衬底上形成浅沟槽隔离（STI）区域，其中所述STI区域被配置为具有大致圆角; 在所述栅极电介质上形成栅极结构; 在SOI晶片上沉积注入层; 在SOI晶片和植入层中执行N型和P型掺杂剂注入之一; 以及加热所述器件以从所述注入层和所述SOI晶片形成源极和漏极区域，其中所述源极和漏极区域具有大于所述SOI晶片的预定厚度的厚度，其中所述栅极电介质位于所述STI区域之下。