公开(公告)号：US20070078288A1

公开(公告)日：2007-04-05

申请号：US11602206

申请日：2006-11-21

Applicant: David Griffiths ,  Ian Little ,  Brian Messenger ,  Ian Reid

Inventor： David Griffiths ,  Ian Little ,  Brian Messenger ,  Ian Reid

IPC: C07C5/327 ,  C07C5/373

CPC classification number: C07C5/48 ,  C07C2523/14 ,  C07C2523/42 ,  C07C2523/44 ,  C07C2523/46 ,  C07C2523/72 ,  C10G2400/20 ,  C10G2400/22 ,  Y02P30/40 ,  C07C11/02

Abstract: A process for the production of an olefin comprising partially combusting in a reaction zone a mixture of a hydrocarbon and an oxygen-containing gas in the presence of a catalyst which is capable of supporting combustion beyond the fuel rich limit of flammability to produce the olefin, wherein the superficial feed velocity of said mixture is at least 250 cm s?-l? at standard temperature and operating pressure with the proviso that where the catalyst is an unsupported catalyst, the superficial feed velocity of said mixture is at least 300 cm s−1 at standard temperature and operating pressure.

Abstract translation: 一种生产烯烃的方法，包括在催化剂存在下在反应区域中部分地燃烧烃和含氧气体的混合物，所述催化剂能够支持超出燃料的燃烧极限以产生烯烃， 其中所述混合物的表面进料速度至少为250cm 3 / 在标准温度和操作压力下，条件是当催化剂是无载体催化剂时，在标准温度和操作压力下，所述混合物的表面进料速度为至少300cm -1。

公开(公告)号：US20050079724A1

公开(公告)日：2005-04-14

申请号：US10605607

申请日：2003-10-13

Applicant: Herbert Ho ,  Mahender Kumar ,  Brian Messenger ,  Michael Steigerwalt

Inventor： Herbert Ho ,  Mahender Kumar ,  Brian Messenger ,  Michael Steigerwalt

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/461 ,  H01L21/762

CPC classification number: H01L21/3081 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76283

Abstract: A method for etching a silicon on insulator (SOI) substrate includes opening a hardmask layer formed on an SOI layer, and etching through the SOI layer, a buried insulator layer underneath the SOI layer, and a bulk silicon layer beneath the buried insulator layer using a single etch step.

Abstract translation: 一种用于蚀刻绝缘体上硅（SOI）衬底的方法，包括：打开形成在SOI层上的硬掩模层，并通过SOI层蚀刻，SOI层下方的掩埋绝缘体层和掩埋绝缘体层下方的体硅层，使用 单个蚀刻步骤。

公开(公告)号：US08692307B2

公开(公告)日：2014-04-08

申请号：US13530519

申请日：2012-06-22

Applicant: Joseph Ervin ,  Brian Messenger ,  Karen A. Nummy ,  Ravi M. Todi

Inventor： Joseph Ervin ,  Brian Messenger ,  Karen A. Nummy ,  Ravi M. Todi

IPC: H01L27/108

CPC classification number: H01L28/60 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

Abstract: Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The structure includes a wafer comprising a substrate, buried insulator layer and a layer of silicon on insulator layer (SOI) having a single crystalline structure throughout the layer. The structure further includes a first plate in the substrate and an insulator layer in direct contact with the first plate. A doped polysilicon is in direct contact with the insulator layer and also in direct contact with the single crystalline structure of the SOI.

Abstract translation: 公开了深沟槽电容器结构和制造方法。 该方法包括在包括衬底，掩埋氧化物层（BOX）和硅（SOI））膜的晶片中形成深沟槽结构。 该结构包括晶片，其包括衬底，掩埋绝缘体层和在整个层中具有单晶结构的绝缘体上硅层（SOI）层。 该结构还包括基板中的第一板和与第一板直接接触的绝缘体层。 掺杂多晶硅与绝缘体层直接接触，并且与SOI的单晶结构直接接触。

公开(公告)号：US08232163B2

公开(公告)日：2012-07-31

申请号：US12916864

申请日：2010-11-01

Applicant: Joseph Ervin ,  Brian Messenger ,  Karen A. Nummy ,  Ravi M. Todi

Inventor： Joseph Ervin ,  Brian Messenger ,  Karen A. Nummy ,  Ravi M. Todi

IPC: H01L21/8242

CPC classification number: H01L28/60 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

Abstract: Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The method further includes forming a plate on a sidewall of the deep trench structure in the substrate by an implant process. The implant processes contaminate exposed edges of the SOI film in the deep trench structure. The method further includes removing the contaminated exposed edges of the SOI film by an etching process to form a void in the SOI film. The method further includes growing epitaxial Si in the void, prior to completing a capacitor structure.

Abstract translation: 公开了深沟槽电容器结构和制造方法。 该方法包括在包括衬底，掩埋氧化物层（BOX）和硅（SOI））膜的晶片中形成深沟槽结构。 该方法还包括通过植入工艺在衬底中的深沟槽结构的侧壁上形成板。 植入工艺污染了深沟槽结构中SOI膜的暴露边缘。 该方法还包括通过蚀刻工艺去除SOI膜的污染的暴露边缘，以在SOI膜中形成空隙。 该方法还包括在完成电容器结构之前在空隙中生长外延Si。

公开(公告)号：US20120104547A1

公开(公告)日：2012-05-03

申请号：US12916864

申请日：2010-11-01

Applicant: JOSEPH ERVIN ,  Brian Messenger ,  Karen A. Nummy ,  Ravi M. Todi

Inventor： JOSEPH ERVIN ,  Brian Messenger ,  Karen A. Nummy ,  Ravi M. Todi

IPC: H01L29/94 ,  H01L21/20

CPC classification number: H01L28/60 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66181 ,  H01L29/945

Abstract: Deep trench capacitor structures and methods of manufacture are disclosed. The method includes forming a deep trench structure in a wafer comprising a substrate, buried oxide layer (BOX) and silicon (SOI) film. The method further includes forming a plate on a sidewall of the deep trench structure in the substrate by an implant process. The implant processes contaminate exposed edges of the SOI film in the deep trench structure. The method further includes removing the contaminated exposed edges of the SOI film by an etching process to form a void in the SOI film. The method further includes growing epitaxial Si in the void, prior to completing a capacitor structure.

Abstract translation: 公开了深沟槽电容器结构和制造方法。 该方法包括在包括衬底，掩埋氧化物层（BOX）和硅（SOI））膜的晶片中形成深沟槽结构。 该方法还包括通过植入工艺在衬底中的深沟槽结构的侧壁上形成板。 植入工艺污染了深沟槽结构中SOI膜的暴露边缘。 该方法还包括通过蚀刻工艺去除SOI膜的污染的暴露边缘，以在SOI膜中形成空隙。 该方法还包括在完成电容器结构之前在空隙中生长外延Si。

公开(公告)号：US07446005B2

公开(公告)日：2008-11-04

申请号：US11433266

申请日：2006-05-12

Applicant: Brian Messenger ,  Renee T. Mo ,  Dominic J. Schepis

Inventor： Brian Messenger ,  Renee T. Mo ,  Dominic J. Schepis

IPC: H01L21/336

CPC classification number: H01L29/66742 ,  H01L29/7842 ,  H01L29/78687

Abstract: A manufacturable way to recess silicon that employs an end point detection method for the recess etch and allows tight tolerances on the recess is described for fabricating a strained raised source/drain layer. The method includes forming a monolayer oxygen and carbon on a surface of a doped semiconductor substrate; forming an epi Si layer atop the doped semiconductor substrate; forming at least one gate region on the epi Si layer; selectively etching exposed portions of the epi layer, not protected by the gate region, stopping on and exposing the doped semiconductor substrate using end point detection; and forming a strained SiGe layer on the exposed doped semiconductor substrate. The strained SiGe layer severs as a raised layer in which source/drain diffusion regions can be subsequently formed.

Abstract translation: 为了制造应变升高的源极/漏极层，描述了用于凹陷蚀刻采用端点检测方法以及允许在凹槽上的紧密公差的硅的可制造方法。 该方法包括在掺杂半导体衬底的表面上形成单层氧和碳; 在掺杂半导体衬底的顶部形成外延Si层; 在外延Si层上形成至少一个栅极区; 选择性地蚀刻未被栅极区域保护的外延层的暴露部分，使用端点检测停止并暴露掺杂半导体衬底; 以及在所述暴露的掺杂半导体衬底上形成应变SiGe层。 应变SiGe层作为凸起层切断，其中可以随后形成源/漏扩散区。

公开(公告)号：US20070115974A1

公开(公告)日：2007-05-24

申请号：US11610705

申请日：2006-12-14

Applicant: Brian Messenger

Inventor： Brian Messenger

IPC: H04L12/56 ,  H04L12/28

CPC classification number: H04Q11/0005 ,  H04L45/00 ,  H04L45/742 ,  H04Q11/0066 ,  H04Q2011/0039

Abstract: An optical network packet classification architecture is disclosed that addresses the packet classification requirements for OC-768 optical routers and beyond. The herein disclosed system is used for ultra-high speed packet classification of optical data at either the serial data stream level for maximum performance, or after it has been converted into parallel words of data. The presently preferred embodiment of the invention provides a system that operates in the receive path, where electronic data are provided by the optical interface to the data framer. The invention incorporates unique features into a traditional optical data framer chip and relies on a complex ASIC to permit the user to differentiate between up to 10,000 different patterns at ultra-high speeds. One purpose of the general purpose system disclosed herein is to eliminate the need for costly and power consumptive content addressable memory systems, or customer pattern specific ASICs, to perform network packet classification. The system operates on a principle of adaptive programmable randomization to permit a differentiation between the input vectors to be made. The invention dramatically reduces the processing burden required by high-speed optical routers or switches.

Abstract translation: 公开了一种解决OC-768光路由器及其以外的分组分类要求的光网络分组分类架构。 本文公开的系统用于在串行数据流级别的光数据的超高速分组分类以获得最大性能，或者在将其转换成并行数据字之后。 本发明的当前优选实施例提供了一种在接收路径中操作的系统，其中电子数据由光学接口提供给数据成帧器。 本发明将独特的特征结合到传统的光学数据成帧器芯片中，并且依赖于复杂的ASIC来允许用户以超高速度区分多达10,000个不同的模式。 本文公开的通用系统的一个目的是消除对昂贵的和耗电的内容可寻址存储器系统或客户模式特定ASIC的需要来执行网络分组分类。 该系统基于自适应可编程随机化的原理运行，以允许要进行的输入向量之间的区分。 本发明大大降低了高速光路由器或交换机所需的处理负担。

公开(公告)号：US20060074268A1

公开(公告)日：2006-04-06

申请号：US11256194

申请日：2005-10-24

Applicant: John Couves ,  David Griffiths ,  Brian Messenger ,  Ian Beattie Reid

Inventor： John Couves ,  David Griffiths ,  Brian Messenger ,  Ian Beattie Reid

IPC: C07C4/02

CPC classification number: B01J23/626 ,  B01J23/56 ,  B01J23/62 ,  C07C5/48 ,  C07C2521/02 ,  C07C2523/08 ,  C07C2523/14 ,  C07C2523/18 ,  C07C2523/44 ,  C07C11/02

Abstract: A process for the production of an olefin from a hydrocarbon, which process comprises: partially combusting the hydrocarbon and an oxygen-containing gas in the presence of a catalyst, characterised in that the catalyst comprises palladium and at least one further metal, said further metal being a Group IIIA, Group IVA, VA or a transition metal.

Abstract translation: 一种从烃生产烯烃的方法，该方法包括：在催化剂存在下部分燃烧烃和含氧气体，其特征在于催化剂包含钯和至少一种其它金属，所述另外的金属 作为IIIA族，IVA族，VA族或过渡金属。

公开(公告)号：US06995094B2

公开(公告)日：2006-02-07

申请号：US10605607

申请日：2003-10-13

Applicant: Herbert L. Ho ,  Mahender Kumar ,  Brian Messenger ,  Michael D. Steigerwalt

Inventor： Herbert L. Ho ,  Mahender Kumar ,  Brian Messenger ,  Michael D. Steigerwalt

IPC: H01L21/302

CPC classification number: H01L21/3081 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76283

Abstract: A method for etching a silicon on insulator (SOI) substrate includes opening a hardmask layer formed on an SOI layer, and etching through the SOI layer, a buried insulator layer underneath the SOI layer, and a bulk silicon layer beneath the buried insulator layer using a single etch step.

Abstract translation: 一种用于蚀刻绝缘体上硅（SOI）衬底的方法，包括：打开形成在SOI层上的硬掩模层，并通过SOI层蚀刻，SOI层下方的掩埋绝缘体层和掩埋绝缘体层下方的体硅层，使用 单个蚀刻步骤。

公开(公告)号：US20070077702A1

公开(公告)日：2007-04-05

申请号：US11539926

申请日：2006-10-10

Applicant: Kangguo Cheng ,  Brian Messenger

Inventor： Kangguo Cheng ,  Brian Messenger

IPC: H01L21/8242 ,  H01L29/788

CPC classification number: H01L29/66181 ,  H01L27/1087 ,  H01L29/945

Abstract: A process is provided for forming a trench capacitor, such as used in a DRAM memory cell, in which the required number of polysilicon deposition steps and planarization steps are reduced. A first region of a first material is formed in the bottom portion of the trench, and a dielectric material for the collar structure is subsequently formed above this region on a portion of the trench sidewalls. A removable material, such as a resist or spin-on glass, is then provided in the trench, overlying the first material and in contact with the lower portion of the collar dielectric material. The upper portion of the collar structure is then removed, after which the removable material is removed to again expose the upper surface of the first region. A second region of a second material, overlying and in contact with the first region, is then formed; the second region has an upper surface below the surface of the substrate. The first and second materials are conducting materials, typically polysilicon. The capacitor thus may be formed with only two polysilicon deposition processes; the interface between the first and second materials is the only interface between conducting materials in the trench.

Abstract translation: 提供了一种用于形成诸如在DRAM存储单元中使用的沟槽电容器的过程，其中所需数量的多晶硅沉积步骤和平坦化步骤被减少。 第一材料的第一区域形成在沟槽的底部，并且随后在沟槽侧壁的一部分上方形成用于套环结构的电介质材料。 然后，在沟槽中提供可移除材料，例如抗蚀剂或旋涂玻璃，覆盖第一材料并与套环电介质材料的下部接触。 然后移除套环结构的上部，之后除去可去除的材料以再次暴露第一区域的上表面。 然后形成覆盖并与第一区域接触的第二材料的第二区域; 第二区域在衬底的表面下方具有上表面。 第一和第二材料是导电材料，通常是多晶硅。 因此，电容器可以仅形成两个多晶硅沉积工艺; 第一和第二材料之间的界面是沟槽中导电材料之间的唯一界面。