-
公开(公告)号：US08040357B1
公开(公告)日：2011-10-18
申请号：US11893418
申请日：2007-08-15
IPC分类号： G09G5/00
CPC分类号： G06T11/40
摘要： Embodiments of the present invention pixel processing system and method provide convenient and efficient processing of pixel information. In one embodiment, quotient-remainder information associated with barycentric coordinate information indicating the location of a pixel is received. In one exemplary implementation quotient-remainder information is associated with barycentric coordinate information through the relationship c divided by dcdx, where c is the barycentric coordinate for a particular edge and dcdx is the derivative of the barycentric coordinate in the screen horizontal direction. The relationship of a pixel with respect to a primitive edge is determined based upon the quotient-remainder information. For example, a positive quotient can indicate a pixel is inside a triangle and a negative quotient can indicate a pixel is outside a triangle. Pixel processing such as shading is performed in accordance with the relationship of the pixel to the primitive.
摘要翻译： 本发明的像素处理系统和方法的实施例提供了对像素信息的方便和有效的处理。 在一个实施例中，接收与指示像素的位置的重心坐标信息相关联的商剩余信息。 在一个示例性实施方案中，商余数信息通过除以dcdx的关系c与重心坐标信息相关联，其中c是特定边缘的重心坐标，dcdx是屏幕水平方向上的重心坐标的导数。 基于商余数信息确定像素与原始边缘的关系。 例如，正商可以指示像素在三角形内，而负商可以指示像素在三角形之外。 根据像素与原图的关系来执行诸如阴影的像素处理。
-
公开(公告)号：US08564598B2
公开(公告)日：2013-10-22
申请号：US12001251
申请日：2007-12-10
IPC分类号： G06T1/00
CPC分类号： G06T11/40
摘要： In a graphics pipeline of a graphics processor, a method for a unified primitive description for rasterization. The method includes receiving a group of primitives from a graphics application, wherein the group includes different types of primitives and the types of primitives include line primitives, point primitives and triangle primitives. For each of the types of primitives, the method includes generating a corresponding parallelogram, wherein the parallelogram has four sides disposed along an x-axis and a y-axis, and computing an inside y-axis mid point and an outside y-axis mid point based on the four sides. The parallelogram is controlled to represent to each of the primitive types respectively by adjusting a location of the inside y-axis mid point or the outside y-axis mid point.
-
13.发明授权Method and system for scalable, dataflow-based, programmable processing of graphics data 有权用于可扩展，基于数据流，可编程处理图形数据的方法和系统公开(公告)号：US06980209B1
公开(公告)日：2005-12-27
申请号：US10172174
申请日：2002-06-14
申请人： Christopher D. S. Donham , Alexander Lev Minkin , Bryon Nordquist , Edward A. Hutchins , Mark Tian , George Easton Scott III
发明人： Christopher D. S. Donham , Alexander Lev Minkin , Bryon Nordquist , Edward A. Hutchins , Mark Tian , George Easton Scott III
CPC分类号： G06T15/005
摘要： A scalable pipelined pixel shader that processes packets of data and preserves the format of each packet at each processing stage. Each packet is an ordered array of data values, at least one of which is an instruction pointer. Each member of the ordered array can be indicative of any type of data. As a packet progresses through the pixel shader during processing, each member of the ordered array can be replaced by a sequence of data values indicative of different types of data (e.g., an address of a texel, a texel, or a partially or fully processed color value). Information required for the pixel shader to process each packet is contained in the packet, and thus the pixel shader is scalable in the sense that it can be implemented in modular fashion to include any number of identical pipelined processing stages and can execute the same program regardless of the number of stages. Preferably, each processing stage is itself scalable, can be implemented to include an arbitrary number of identical pipelined instruction execution stages known as microblenders, and can execute the same program regardless of the number of microblenders. The current value of the instruction pointer (IP) in a packet determines the next instruction to be executed on the data contained in the packet. Any processing unit can change the instruction that will be executed by a subsequent processing unit by modifying the IP (and/or condition codes) of a packet that it asserts to the subsequent processing unit. Other aspects of the invention include graphics processors (each including a pixel shader configured in accordance with the invention), methods and systems for generating packets of data for processing in accordance with the invention, and methods for pipelined processing of packets of data.
摘要翻译： 可扩展的流水线像素着色器，可处理数据包，并在每个处理阶段保留每个数据包的格式。 每个数据包是有序的数据值阵列，其中至少有一个是指令指针。 有序数组的每个成员可以指示任何类型的数据。 随着分组在处理期间通过像素着色器进行，有序阵列的每个成员可以被指示不同类型的数据的数据值序列（例如，纹素，纹素，或部分或完全处理的地址 颜色值）。 像素着色器处理每个数据包所需的信息包含在数据包中，因此像素着色器在可以以模块化方式实现以包括任意数量的相同流水线处理级并且可以执行相同的程序的意义上是可缩放的 的阶段数。 优选地，每个处理阶段本身是可扩展的，可以被实现为包括任意数量的称为微型混合器的相同的流水线指令执行阶段，并且可以执行相同的程序，而不管微型混合器的数量。 分组中的指令指针（IP）的当前值确定要对包含在分组中的数据执行的下一条指令。 任何处理单元可以通过修改后续处理单元确定的分组的IP（和/或条件代码）来改变将由后续处理单元执行的指令。 本发明的其他方面包括图形处理器（每个包括根据本发明配置的像素着色器），用于生成根据本发明进行处理的数据分组的方法和系统，以及用于流水线处理数据分组的方法。
-
公开(公告)号：US08441497B1
公开(公告)日：2013-05-14
申请号：US11890838
申请日：2007-08-07
CPC分类号： G06T15/005 , G06T15/20
摘要： Vertex data can be accessed for a graphics primitive. The vertex data includes homogeneous coordinates for each vertex of the primitive. The homogeneous coordinates can be used to determine perspective-correct barycentric coordinates that are normalized by the area of the primitive. The normalized perspective-correct barycentric coordinates can be used to determine an interpolated value of an attribute for the pixel. These operations can be performed using adders and multipliers implemented in hardware.
摘要翻译： 可以为图形原语访问顶点数据。 顶点数据包括基元的每个顶点的均匀坐标。 均匀坐标可用于确定通过原语区域归一化的透视校正重心坐标。 可以使用归一化的透视校正重心坐标来确定像素的属性的内插值。 这些操作可以使用在硬件中实现的加法器和乘法器执行。
-
15.发明授权Reducing instruction execution passes of data groups through a data operation unit 有权通过数据操作单元减少数据组的指令执行次数公开(公告)号：US08856499B1
公开(公告)日：2014-10-07
申请号：US11893615
申请日：2007-08-15
申请人： Michael J. M. Toksvig , Justin M. Mahan , Edward A. Hutchins , Tyson J. Bergland , James T. Battle , Ashok Srinivasan
发明人： Michael J. M. Toksvig , Justin M. Mahan , Edward A. Hutchins , Tyson J. Bergland , James T. Battle , Ashok Srinivasan
CPC分类号： G06F9/3836 , G06F9/321 , G06F9/381 , G06F9/383
摘要： An apparatus is disclosed. The apparatus comprises an instruction mapping table, which includes a plurality of instruction counts and a plurality of instruction pointers each corresponding with one of the instruction counts. Each instruction pointer identifies a next instruction for execution. Further, each instruction count specifies a number of instructions to execute beginning with the next instruction. The apparatus also has a data operation unit adapted to receive a data group and adapted to execute on the received data group the number of instructions specified by a current instruction count of the instruction mapping table beginning with the next instruction identified by a current instruction pointer of the instruction mapping table before proceeding with another data group.
摘要翻译： 公开了一种装置。 该装置包括指令映射表，其包括多个指令计数和多个指令指针，每个指令指针与指令计数之一相对应。 每个指令指针标识下一个执行指令。 此外，每个指令计数指定从下一条指令开始执行的指令数。 该装置还具有数据操作单元，该数据操作单元适于接收数据组并适于在接收到的数据组上执行指令映射表的当前指令计数指定的指令数，该指令开始于由当前指令指针 在进行另一个数据组之前的指令映射表。
-
公开(公告)号：US09024957B1
公开(公告)日：2015-05-05
申请号：US11893427
申请日：2007-08-15
CPC分类号： G06F8/61 , G06F9/44557 , G06T15/005
摘要： A method for loading a shader program from system memory into GPU memory. The method includes accessing the shader program in system memory of a computer system. A DMA transfer of the shader program from system memory into GPU memory is performed such that the shader program is loaded into GPU memory in an address independent manner.
摘要翻译： 将着色器程序从系统内存加载到GPU内存的方法。 该方法包括访问计算机系统的系统存储器中的着色器程序。 着色器程序从系统内存到GPU存储器的DMA传输被执行，使得着色器程序以独占于地址的方式被加载到GPU存储器中。
-
公开(公告)号：US08599208B2
公开(公告)日：2013-12-03
申请号：US11893622
申请日：2007-08-15
申请人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J. M. Toksvig , Justin M. Mahan
发明人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J. M. Toksvig , Justin M. Mahan
CPC分类号： G09G5/363 , G06F9/30098 , G06F9/3879 , G06T1/20 , G06T15/005
摘要： An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be read from any of the registers, regardless of which of the pixels is being operated on by the ALUs. However, when writing results of the ALU operations, only some of the global registers are candidates to be written to, depending on the pixel number. Accordingly, overwriting of data is prevented.
-
公开(公告)号：US07408553B1
公开(公告)日：2008-08-05
申请号：US11305483
申请日：2005-12-15
IPC分类号： G06T11/40
CPC分类号： G06T11/40
摘要： Systems and methods for identifying pixels that are inside a two-dimensional path may be used to fill the path. The path is segmented and a point in space is identified that is used to generate a triangle fan, where each triangle in the fan is formed by one of the segments of the path and the point. Locations in a winding buffer are updated for each pixel that is within a triangle of the triangle fan. The resulting winding buffer indicates the pixels that are inside the two-dimensional path. The winding buffer may be used to fill the path.
摘要翻译： 用于识别二维路径内的像素的系统和方法可以用于填充路径。 路径被分割，并且识别用于产生三角形风扇的空间中的点，其中风扇中的每个三角形由路径和点之一的一个段形成。 针对三角形风扇三角形内的每个像素，更新绕组缓冲区中的位置。 得到的卷绕缓冲器指示二维路径内的像素。 卷绕缓冲器可用于填充路径。
-
公开(公告)号：US08775777B2
公开(公告)日：2014-07-08
申请号：US11893584
申请日：2007-08-15
申请人： Tyson J. Bergland , Craig M. Okruhlica , Michael J. M. Toksvig , Justin M. Mahan , Edward A. Hutchins
发明人： Tyson J. Bergland , Craig M. Okruhlica , Michael J. M. Toksvig , Justin M. Mahan , Edward A. Hutchins
IPC分类号： G06F15/76
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/30167 , G06F9/30185 , G06F9/3853 , G06F9/3885 , G06T15/005
摘要： Sourcing immediate values from a very long instruction word includes determining if a VLIW sub-instruction expansion condition exists. If the sub-instruction expansion condition exists, operation of a portion of a first arithmetic logic unit component is minimized. In addition, a part of a second arithmetic logic unit component is expanded by utilizing a block of a very long instruction word, which is normally utilized by the first arithmetic logic unit component, for the second arithmetic logic unit component if the sub-instruction expansion condition exists.
摘要翻译： 从非常长的指令字中采集即时值包括确定是否存在VLIW子指令扩展条件。 如果存在子指令扩展条件，则将第一算术逻辑单元组件的一部分的操作最小化。 此外，如果副指令扩展，则第二算术逻辑单元组件的一部分通过利用第二算术逻辑单元组件通常由第一算术逻辑单元组件使用的非常长的指令字的块来扩展 条件存在。
-
20.发明授权公开(公告)号：US08314803B2
公开(公告)日：2012-11-20
申请号：US11893499
申请日：2007-08-15
申请人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J. M. Toksvig , Justin M. Mahan
发明人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J. M. Toksvig , Justin M. Mahan
CPC分类号： G06T1/20
摘要： An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock cycle, the buffer stores one row of a series of rows of pixel data. A deserializer deserializes the rows of pixel data before the pixel data is placed in the buffer. After the buffer accumulates all rows of pixel data for a pixel, then the pixel data for the pixel can be operated on by the ALUs.
摘要翻译： 图形处理器单元流水线中的算术逻辑级包括多个算术逻辑单元（ALU）和至少一个存储一组像素的像素数据的缓冲器。 每个时钟周期，缓冲存储一行一系列像素数据。 在将像素数据放置在缓冲器中之前，解串器反序列化像素数据行。 在缓冲器累积像素的所有像素数据行之后，可以由ALU操作像素的像素数据。
-
-
-
-
-
-
-
-
-
搜索结果
64 条记录 (耗时 0.026 秒)
