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公开(公告)号：US08775777B2
公开(公告)日：2014-07-08
申请号：US11893584
申请日：2007-08-15
申请人： Tyson J. Bergland , Craig M. Okruhlica , Michael J. M. Toksvig , Justin M. Mahan , Edward A. Hutchins
发明人： Tyson J. Bergland , Craig M. Okruhlica , Michael J. M. Toksvig , Justin M. Mahan , Edward A. Hutchins
IPC分类号： G06F15/76
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/30167 , G06F9/30185 , G06F9/3853 , G06F9/3885 , G06T15/005
摘要： Sourcing immediate values from a very long instruction word includes determining if a VLIW sub-instruction expansion condition exists. If the sub-instruction expansion condition exists, operation of a portion of a first arithmetic logic unit component is minimized. In addition, a part of a second arithmetic logic unit component is expanded by utilizing a block of a very long instruction word, which is normally utilized by the first arithmetic logic unit component, for the second arithmetic logic unit component if the sub-instruction expansion condition exists.
摘要翻译： 从非常长的指令字中采集即时值包括确定是否存在VLIW子指令扩展条件。 如果存在子指令扩展条件，则将第一算术逻辑单元组件的一部分的操作最小化。 此外，如果副指令扩展，则第二算术逻辑单元组件的一部分通过利用第二算术逻辑单元组件通常由第一算术逻辑单元组件使用的非常长的指令字的块来扩展 条件存在。
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2.发明授权公开(公告)号：US08314803B2
公开(公告)日：2012-11-20
申请号：US11893499
申请日：2007-08-15
申请人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J. M. Toksvig , Justin M. Mahan
发明人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J. M. Toksvig , Justin M. Mahan
CPC分类号： G06T1/20
摘要： An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock cycle, the buffer stores one row of a series of rows of pixel data. A deserializer deserializes the rows of pixel data before the pixel data is placed in the buffer. After the buffer accumulates all rows of pixel data for a pixel, then the pixel data for the pixel can be operated on by the ALUs.
摘要翻译： 图形处理器单元流水线中的算术逻辑级包括多个算术逻辑单元（ALU）和至少一个存储一组像素的像素数据的缓冲器。 每个时钟周期，缓冲存储一行一系列像素数据。 在将像素数据放置在缓冲器中之前，解串器反序列化像素数据行。 在缓冲器累积像素的所有像素数据行之后，可以由ALU操作像素的像素数据。
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公开(公告)号：US08599208B2
公开(公告)日：2013-12-03
申请号：US11893622
申请日：2007-08-15
申请人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J. M. Toksvig , Justin M. Mahan
发明人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J. M. Toksvig , Justin M. Mahan
CPC分类号： G09G5/363 , G06F9/30098 , G06F9/3879 , G06T1/20 , G06T15/005
摘要： An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be read from any of the registers, regardless of which of the pixels is being operated on by the ALUs. However, when writing results of the ALU operations, only some of the global registers are candidates to be written to, depending on the pixel number. Accordingly, overwriting of data is prevented.
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公开(公告)号：US20090049276A1
公开(公告)日：2009-02-19
申请号：US11893584
申请日：2007-08-15
申请人： Tyson J. Bergland , Craig M. Okruhlica , Michael J.M. Toksvig , Justin M. Mahan , Edward A. Hutchins
发明人： Tyson J. Bergland , Craig M. Okruhlica , Michael J.M. Toksvig , Justin M. Mahan , Edward A. Hutchins
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/30167 , G06F9/30185 , G06F9/3853 , G06F9/3885 , G06T15/005
摘要： Sourcing immediate values from a very long instruction word includes determining if a VLIW sub-instruction expansion condition exists. If the sub-instruction expansion condition exists, operation of a portion of a first arithmetic logic unit component is minimized. In addition, a part of a second arithmetic logic unit component is expanded by utilizing a block of a very long instruction word, which is normally utilized by the first arithmetic logic unit component, for the second arithmetic logic unit component if the sub-instruction expansion condition exists.
摘要翻译： 从非常长的指令字中采集即时值包括确定是否存在VLIW子指令扩展条件。 如果存在子指令扩展条件，则将第一算术逻辑单元组件的一部分的操作最小化。 此外，如果副指令扩展，则第二算术逻辑单元组件的一部分通过利用第二算术逻辑单元组件通常由第一算术逻辑单元组件使用的非常长的指令字的块来扩展 条件存在。
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5.发明申请公开(公告)号：US20110254848A1
公开(公告)日：2011-10-20
申请号：US11893499
申请日：2007-08-15
申请人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J.M. Toksvig , Justin M. Mahan
发明人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J.M. Toksvig , Justin M. Mahan
IPC分类号： G06T1/00
CPC分类号： G06T1/20
摘要： An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock cycle, the buffer stores one row of a series of rows of pixel data. A deserializer deserializes the rows of pixel data before the pixel data is placed in the buffer. After the buffer accumulates all rows of pixel data for a pixel, then the pixel data for the pixel can be operated on by the ALUs.
摘要翻译： 图形处理器单元流水线中的算术逻辑级包括多个算术逻辑单元（ALU）和至少一个存储一组像素的像素数据的缓冲器。 每个时钟周期，缓冲存储一行一系列像素数据。 在将像素数据放置在缓冲器中之前，解串器反序列化像素数据行。 在缓冲器累积像素的所有像素数据行之后，可以由ALU操作像素的像素数据。
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6.发明申请Shared readable and writeable global values in a graphics processor unit pipeline 有权在图形处理器单元管道中共享可读和可写的全局值公开(公告)号：US20090046103A1
公开(公告)日：2009-02-19
申请号：US11893622
申请日：2007-08-15
申请人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J.M. Toksvig , Justin M. Mahan
发明人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J.M. Toksvig , Justin M. Mahan
CPC分类号： G09G5/363 , G06F9/30098 , G06F9/3879 , G06T1/20 , G06T15/005
摘要： An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be read from any of the registers, regardless of which of the pixels is being operated on by the ALUs. However, when writing results of the ALU operations, only some of the global registers are candidates to be written to, depending on the pixel number. Accordingly, overwriting of data is prevented.
摘要翻译： 图形处理器单元中的算术逻辑级包括算术逻辑单元（ALU）和全局寄存器。 这些寄存器包含一组像素的全局值。 可以从任何寄存器读取全局值，而不管由哪个像素由ALU操作。 然而，当写入ALU操作的结果时，根据像素数目，只有一些全局寄存器被写入候选。 因此，防止了数据的重写。
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7.发明授权Reducing instruction execution passes of data groups through a data operation unit 有权通过数据操作单元减少数据组的指令执行次数公开(公告)号：US08856499B1
公开(公告)日：2014-10-07
申请号：US11893615
申请日：2007-08-15
申请人： Michael J. M. Toksvig , Justin M. Mahan , Edward A. Hutchins , Tyson J. Bergland , James T. Battle , Ashok Srinivasan
发明人： Michael J. M. Toksvig , Justin M. Mahan , Edward A. Hutchins , Tyson J. Bergland , James T. Battle , Ashok Srinivasan
CPC分类号： G06F9/3836 , G06F9/321 , G06F9/381 , G06F9/383
摘要： An apparatus is disclosed. The apparatus comprises an instruction mapping table, which includes a plurality of instruction counts and a plurality of instruction pointers each corresponding with one of the instruction counts. Each instruction pointer identifies a next instruction for execution. Further, each instruction count specifies a number of instructions to execute beginning with the next instruction. The apparatus also has a data operation unit adapted to receive a data group and adapted to execute on the received data group the number of instructions specified by a current instruction count of the instruction mapping table beginning with the next instruction identified by a current instruction pointer of the instruction mapping table before proceeding with another data group.
摘要翻译： 公开了一种装置。 该装置包括指令映射表，其包括多个指令计数和多个指令指针，每个指令指针与指令计数之一相对应。 每个指令指针标识下一个执行指令。 此外，每个指令计数指定从下一条指令开始执行的指令数。 该装置还具有数据操作单元，该数据操作单元适于接收数据组并适于在接收到的数据组上执行指令映射表的当前指令计数指定的指令数，该指令开始于由当前指令指针 在进行另一个数据组之前的指令映射表。
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公开(公告)号：US09183607B1
公开(公告)日：2015-11-10
申请号：US11893431
申请日：2007-08-15
申请人： Justin M. Mahan , Edward A. Hutchins , Kevin P. Acken , Michael J. M. Toksvig , Christopher D. S. Donham
发明人： Justin M. Mahan , Edward A. Hutchins , Kevin P. Acken , Michael J. M. Toksvig , Christopher D. S. Donham
CPC分类号： G06T15/005 , G06T1/60 , G06T11/40
摘要： A method in system for latency buffered scoreboarding in a graphics pipeline of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive to generate a plurality pixels related to the graphics primitive. An ID stored to account for an initiation of parameter evaluation for each of the plurality of pixels as the pixels are transmitted to a subsequent stage of the graphics processor. A buffer is used to store the fragment data resulting from the parameter evaluation for each of the plurality of pixels by the subsequent stage. The ID and the fragment data from the buffering are compared to determine whether they correspond to one another. The completion of parameter evaluation for each of the plurality of pixels is accounted for when the ID and the fragment data match and as the fragment data is written to a memory.
摘要翻译： 一种用于在图形处理器的图形管线中等待时间缓冲记分板的系统中的方法。 该方法包括在图形处理器的光栅级中接收用于光栅化的图形基元，并且对图形基元进行光栅化以生成与图形基元相关的多个像素。 存储的ID用于当像素被传送到图形处理器的后续阶段时考虑对于多个像素中的每一个的参数评估的启动。 缓冲器用于存储由后续阶段的多个像素中的每一个的参数评估产生的片段数据。 比较来自缓冲的ID和片段数据以确定它们是否彼此对应。 当ID和片段数据匹配并且片段数据被写入存储器时，对多个像素中的每一个的参数评估的完成进行了说明。
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公开(公告)号：US08441497B1
公开(公告)日：2013-05-14
申请号：US11890838
申请日：2007-08-07
CPC分类号： G06T15/005 , G06T15/20
摘要： Vertex data can be accessed for a graphics primitive. The vertex data includes homogeneous coordinates for each vertex of the primitive. The homogeneous coordinates can be used to determine perspective-correct barycentric coordinates that are normalized by the area of the primitive. The normalized perspective-correct barycentric coordinates can be used to determine an interpolated value of an attribute for the pixel. These operations can be performed using adders and multipliers implemented in hardware.
摘要翻译： 可以为图形原语访问顶点数据。 顶点数据包括基元的每个顶点的均匀坐标。 均匀坐标可用于确定通过原语区域归一化的透视校正重心坐标。 可以使用归一化的透视校正重心坐标来确定像素的属性的内插值。 这些操作可以使用在硬件中实现的加法器和乘法器执行。
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公开(公告)号：US08594441B1
公开(公告)日：2013-11-26
申请号：US11520144
申请日：2006-09-12
CPC分类号： G06T9/00 , H04N1/646 , H04N19/124 , H04N19/136 , H04N19/186
摘要： Image-based data, such as a block of texel data, is accessed. The data includes sets of color component values. A luminance value is computed for each set of color components values, generating a range of luminance values. A first set and a second set of color component values that correspond to the minimum and maximum luminance values are selected from the sets of color component values. A third set of color component values can be mapped to an index that identifies how the color component values of the third set can be decoded using the color component values of the first and second sets. The index value is selected by determining where the luminance value for the third set lies in the range of luminance values.
摘要翻译： 访问基于图像的数据，例如一组纹素数据。 数据包括彩色分量值集合。 为每组颜色分量值计算亮度值，产生亮度值范围。 从颜色分量值的集合中选择对应于最小和最大亮度值的第一组和第二组颜色分量值。 可以将第三组颜色分量值映射到识别如何使用第一和第二组的颜色分量值来解码第三组的颜色分量值的索引。 通过确定第三组的亮度值位于亮度值的范围内来选择索引值。
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