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公开(公告)号：US5381445A
公开(公告)日：1995-01-10
申请号：US55473
申请日：1993-05-03
申请人： John E. Hershey , Menahem Lowy , Lionel M. Levinson , Amer A. Hassan , Richard L. Frey , Kenneth B. Welles, II , Michael Gdula , Robert J. Wojnarowski
发明人： John E. Hershey , Menahem Lowy , Lionel M. Levinson , Amer A. Hassan , Richard L. Frey , Kenneth B. Welles, II , Michael Gdula , Robert J. Wojnarowski
CPC分类号： G01S5/0009 , F42B12/36 , F42B12/365 , G01S5/06
摘要： A munitions cartridge transmitter capable of emitting an electromagnetic signal after discharge from a cartridge propelling device comprises a signal generator, an electromagnetic signal transmitter coupled to the generator, an antenna coupled to the transmitter, and a hollow cartridge for housing the generator, the transmitter, and the antenna. The transmitter is energized after discharge of the cartridge propelling device by a power source contained in the cartridge.
摘要翻译： 一种能够在从暗盒推进装置排放之后发出电磁信号的弹药盒式发射器包括信号发生器，耦合到发生器的电磁信号发射器，耦合到发射器的天线以及用于容纳发生器的中空滤芯， 和天线。 在通过盒中包含的电源将墨盒驱动装置排出之后，变送器通电。
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12.发明授权Integrated circuit packaging configuration for rapid customized design and unique test capability 失效集成电路封装配置，快速定制设计和独特的测试能力
公开(公告)号：US5214655A
公开(公告)日：1993-05-25
申请号：US784094
申请日：1991-10-28
IPC分类号： G01R31/3185 , H01L23/538
CPC分类号： H01L23/5382 , G01R31/318505 , H01L2924/0002 , H01L2924/3011
摘要： A packaged electronics system, having respective portions each with respective input and output ports, and having interconnection busses between certain of these ports, is tested as follows. Each input port has a set of first transmission gates associated therewith for selectively disconnecting it during testing from the end of each interconnection bus connected bit during normal operation. Each input port has a second set of transmission gates associated therewith for selectively applying test vectors thereto during testing as provided in parallel form from a serially loaded shift register. Each output port connects to the input connections of a respective set of tristate drivers for selectively applying its output signals at relatively low source impedance to at least one interconnection bus connected from the output connections of that set of tristate drivers. A shift register converts the signals appearing in parallel at least one end of each interconnection bus to a concatenation of test results in serial form.
摘要翻译： 具有相应部分的封装电子系统各自具有相应的输入和输出端口，并且在这些端口中的某些端口之间具有互连总线，如下进行测试。 每个输入端口具有与其相关联的一组第一传输门，用于在正常操作期间从每个互连总线连接的位的端部进行测试时选择性地断开它。 每个输入端口具有与之相关联的第二组传输门，用于在测试期间选择性地将测试向量应用于串行装载的移位寄存器的并行形式。 每个输出端口连接到相应组的三态驱动器的输入连接，用于选择性地将其输出信号以相对低的源阻抗施加到从该组三态驱动器的输出连接连接的至少一个互连总线。 移位寄存器将并联出现的每个互连总线的至少一端的信号以串行形式连接到测试结果。
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公开(公告)号：US4392068A
公开(公告)日：1983-07-05
申请号：US284157
申请日：1981-07-17
CPC分类号： H03H19/002
摘要： A capacitive commutating filter provides a D. C. output voltage of amplitude responsive to the amplitude of an input waveform having a frequency substantially equal to the operating frequency of the filter. The filter operating frequency is established by a digital signal. The filter input is selectively and cyclically connected through N input resistances, wherein N is an integer greater than zero, to adjacently progressive N ones of (2N+1) nodes, each having one of (2N+1) capacitive filter elements connected to ground potential. The equilibrium voltages across the capacitive filter elements, established during the N/(2N+1) segments of the input waveform during which each capacitor is connected to the input, are coupled to one set each of maximum-positive-polarity and maximum-negative-polarity diodes, for placing the maximum and minimum filter capacitive element voltages at respective ones of the inverting and non-inverting inputs of a differential amplifier, having the output thereof forming the filter output.
摘要翻译： 电容换向滤波器响应于具有基本上等于滤波器的工作频率的频率的输入波形的振幅，提供D.C输出的幅度电压。 滤波器工作频率由数字信号建立。 滤波器输入通过N个输入电阻（其中N是大于零的整数）选择性地和循环地连接到（2N + 1）个节点的相邻行进的N个（每个具有连接到地的（2N + 1）个电容滤波器元件之一 潜在。 在每个电容器连接到输入端的输入波形的N /（2N + 1）段期间建立的电容滤波器元件之间的平衡电压被耦合到每组最大正极性和最大负值 极性二极管，用于将最大和最小滤波电容元件电压放置在差分放大器的反相和非反相输入的相应位置处，其输出形成滤波器输出。
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14.发明授权Protocol and mechanism for mutter mode communication for stationary master tracking unit 失效静态主跟踪单元的嘟嘟模式通信协议和机制
公开(公告)号：US5608412A
公开(公告)日：1997-03-04
申请号：US484751
申请日：1995-06-07
IPC分类号： G01C21/00 , B61L25/02 , G01S1/00 , G01S1/04 , G01S5/00 , G01S5/14 , G01S19/42 , G08B25/04 , G08G1/127 , H04B7/185 , H04B7/212 , H04L12/28 , H04L12/56 , G01S3/02
CPC分类号： H04W64/00 , B61L25/021 , B61L25/025 , G01S1/045 , G01S5/0027 , G08G1/127 , H04B7/18545 , H04B7/18576 , B61L2205/04 , G01S19/09 , G01S19/16 , H04W84/12
摘要： A local area network (LAN) of tracked mobile assets which are temporarily located in an area having a high density of mobile assets, such as a railway yard, employs a stationary master tracking unit that is responsible for communicating with mobile tracking units affixed to the mobile assets and transmitting information to a central station. The stationary master tracking unit may be mounted at an elevation, as on a pole, and single or multiple stationary master tracking units may exist in the same vicinity. Each stationary master tracking unit has a constant supply of power and communicates with the central station by way of either satellites or dedicated land line connection. A protocol is provided for communicating between the Stationary master tracking unit and the mobile tracking units. The protocol provides a mechanism for acquiring new mobile tracking units entering the railway yard and a mechanism for releasing mobile tracking units leaving the railway yard.
摘要翻译： 临时位于具有高密度移动资产的区域（例如铁路场地）中的被跟踪的移动资产的局域网（LAN）采用静态主跟踪单元，其负责与固定到移动资产的移动跟踪单元进行通信 移动资产和向中心站发送信息。 固定主跟踪单元可以安装在高度上，如杆上，并且单个或多个静止主跟踪单元可以存在于相同的附近。 每个静态主跟踪单元具有恒定的功率供应，并通过卫星或专用陆线连接与中心站通信。 提供了用于在固定主跟踪单元和移动跟踪单元之间进行通信的协议。 该协议提供了一种获取进入铁路场地的新移动跟踪单元的机制，以及用于发布离开铁路场地的移动跟踪单元的机制。
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15.发明授权Adaptive estimation of phase or delay for both leading and lagging phase shifts 失效对相位或滞后相移的相位或延迟进行自适应估计
公开(公告)号：US5124656A
公开(公告)日：1992-06-23
申请号：US589355
申请日：1990-09-28
IPC分类号： G01R25/00
CPC分类号： G01R25/00
摘要： Apparatus for measuring or compensating for phase or time delay between a reference signal and a desired signal produces an approximate error signal by differentially summing the desired and reference signals. The appoximate error signal is then used, in a feedback loop, to control application of an adaptive delay to each of the reference and desired signals. The total lead or lag difference is represented by the difference between the two delays applied to the reference and desired signals, respectively. The phase or time delay measurement or compensation arrangements may be applied to linear variable differential transformers, synchronous AM detectors, zero crossing detectors and phase locked loops. Variations on this basic technique can yield substantially exact measurement or compensation. The invention is applicable to sampling arrangements including oversampling/decimation or interpolation/decimation to increase compensation accuracy to any desired degree.
摘要翻译： 用于测量或补偿参考信号和期望信号之间的相位或时间延迟的装置通过对期望参考信号进行差分求和来产生近似误差信号。 然后在反馈环路中使用近似误差信号来控制对每个参考和期望信号的自适应延迟的应用。 总引线或滞后差分别由施加到基准信号和期望信号的两个延迟之间的差异表示。 相位或时间延迟测量或补偿布置可以应用于线性可变差分变压器，同步AM检测器，过零检测器和锁相环。 这种基本技术的变化可以产生实质上精确的测量或补偿。 本发明适用于包括过采样/抽取或插值/抽取的采样布置，以将补偿精度提高到任何期望的程度。
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16.发明授权Testing of integrated circuits including internal test circuitry and using token passing to select testing ports 失效测试集成电路，包括内部测试电路，并使用令牌传递来选择测试端口
公开(公告)号：US5119378A
公开(公告)日：1992-06-02
申请号：US513636
申请日：1990-04-24
IPC分类号： G01R31/3185
CPC分类号： G01R31/318561
摘要： Built-in test circuitry, which is appropriate for monolithic integrated circuit chips that are to be connected in a plural-chip package, uses electronic token passing to select one of the test input ports in the circuitry to be tested for application of test input vectors. The built-in test circuitry also uses electronic token passing to select one of the test output ports in the circuitry to be tested from which test results are to be supplied. Methods for testing based on these token passing procedures are described.
摘要翻译： 内置测试电路，适用于要连接在多芯片封装中的单片集成电路芯片，使用电子令牌传递来选择要测试的电路中的一个测试输入端口，以应用测试输入向量 。 内置测试电路还使用电子令牌传递来选择要供应的测试结果的待测电路中的一个测试输出端口。 描述了基于这些令牌传递过程的测试方法。
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17.发明授权Apparatus for packaging integrated circuit chips employing a polymer film overlay layer 失效用于封装采用聚合物膜覆盖层的集成电路芯片的装置
公开(公告)号：US5094709A
公开(公告)日：1992-03-10
申请号：US516895
申请日：1990-04-26
IPC分类号： H01L21/00 , H01L21/56 , H01L21/58 , H01L23/31 , H01L23/538
CPC分类号： H01L24/27 , H01L21/56 , H01L21/67121 , H01L23/3164 , H01L23/5389 , H01L24/75 , H01L24/83 , H01L2224/2919 , H01L2224/75315 , H01L2224/8319 , H01L2224/8385 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/14
摘要： A method and apparatus are provided for disposing a polymer film on an irregularly-shaped substrate at relatively high temperatures. In particular, the method and apparatus of the present invention provide a system for the packaging of very large scale integrated circuit chips. The system of the present invention particularly solves problems associated with high temperature processing and problems associated with the highly irregular surfaces that result. Nonetheless, the resultant product is capable of being fashioned into circuit chip systems which are independently testable and which may be reconfigured after testing by removal of the polymer film itself.
摘要翻译： 提供了一种用于在较高温度下将聚合物膜设置在不规则形状的基底上的方法和装置。 特别地，本发明的方法和装置提供了一种用于包装非常大规模集成电路芯片的系统。 本发明的系统特别地解决了与高温处理相关的问题和与导致的高度不规则的表面有关的问题。 然而，所得产品能够被制成可独立测试的电路芯片系统，并且可以在通过去除聚合物膜本身进行测试之后重新配置。
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18.发明授权Method for packaging integrated circuit chips employing a polymer film overlay layer 失效使用聚合物膜覆盖层封装集成电路芯片的方法
公开(公告)号：US4933042A
公开(公告)日：1990-06-12
申请号：US240367
申请日：1988-08-30
IPC分类号： H01L21/00 , H01L21/56 , H01L21/58 , H01L23/31 , H01L23/538
CPC分类号： H01L24/83 , H01L21/56 , H01L21/67121 , H01L23/3164 , H01L23/5389 , H01L24/75 , H01L2224/2919 , H01L2224/75315 , H01L2224/8319 , H01L2224/8385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/14 , Y10T156/1092
摘要： A method and apparatus are provided for disposing a polymer film on an irregularly-shaped substrate at relatively high temperatures. In particular, the method and apparatus of the present invention provide a system for the packaging of very large scale intergrated circuit chips. The system of the present invention particularly solves problems associated with high temperature processing and problems associated with the highly irregular surfaces that result. Nonetheless, the resultant product is capable of being fashioned into circuit chip systems which are independently testable and which may be reconfigured after testing by removal of the polymer film itself.
摘要翻译： 提供了一种用于在较高温度下将聚合物膜设置在不规则形状的基底上的方法和装置。 特别地，本发明的方法和装置提供了一种用于包装非常大规模的集成电路芯片的系统。 本发明的系统特别地解决了与高温处理相关的问题和与导致的高度不规则的表面有关的问题。 然而，所得产品能够被制成可独立测试的电路芯片系统，并且可以在通过去除聚合物膜本身进行测试之后重新配置。
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公开(公告)号：US4835704A
公开(公告)日：1989-05-30
申请号：US947461
申请日：1986-12-29
IPC分类号： G03F1/00 , G03F1/08 , G03F7/20 , H01L21/00 , H01L21/027 , H01L21/30 , H01L21/3213 , H01L21/60 , H01L21/768 , H01L21/82 , H01L23/538 , H05K3/00
CPC分类号： H01L24/25 , G03F7/704 , H01L21/6715 , H01L21/768 , H01L23/5389 , H01L24/24 , H01L24/75 , H01L24/76 , H01L2224/18 , H01L2224/75 , H01L2224/75753 , H01L2224/758 , H01L2224/759 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , Y10S148/093 , Y10S430/146
摘要： An adaptive method and system are disclosed for providing high density interconnections of very large scale integrated circuits on a substrate. The procedure is performed in four basic steps: first an artwork representation for the interconnections of the integrated circuits is generated. This artwork representation is stored in a computer data base and assumes the integrated circuits to be at predetermined ideal locations and positions on the substrate. Second, using imaging, the actual positions of each integrated circuit on the substrate are determined. The actual positions of the integrated circuits are compared with their ideal positions to compute an offset and rotation for each integrated circuit on the substrate. Third, the computed offsets and rotations are then used to modify the artwork representation stored in the data base to account for the actual locations and positions of the integrated circuits on the substrate. Finally, the modified artwork representation is used to drive a direct writing laser lithography system that actually forms the high density interconnections of the integrated circuits on the substrate. The artwork representations are stored in computer data bases in vector form to minimize storage requirements. The laser beam produced by the lithography system is raster scanned on the substrate. Modulation of the laser beam is controlled by the real time conversion of the vector representation of the modified artwork to be a bit mapped representation. To assure accurate formations of the interconnects, a feedback alignment system is used to accurately position the laser beam throughout its raster scan.
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20.发明授权Television frame synchronizer with independently controllable input/output rates 失效电视帧同步器具有可独立控制的输入/输出速率
公开(公告)号：US4646151A
公开(公告)日：1987-02-24
申请号：US697601
申请日：1985-02-01
CPC分类号： H04N5/0736
摘要： A frame synchronizer having broad applicability in television systems is particularly adapted for use in a chrominance time-compressed, luminance bandwidth reduced television system. The frame synchronizer, which separates the composite video signal into its component parts and thereby minimizes the dynamic range required to digitize the signal, demodulates the chrominance signal into its quadrature components and separates the luminance signal. The synchronization signal in the composite video signal generates slave distribution signals and slave horizontal and vertical addresses. The separated chrominance quadrature components and the luminance signal are digitized and, along with the slave distribution signals and the slave horizontal and vertical addresses, are temporarily stored in first-in, first-out memories which provide independent buffering and thereby accommodate a high degree of mismatch between master and slave timing. The chrominance and luminance data are accumulated in distribution registers and transferred to write registers which provide the data input to a frame buffer memory. Master distribution and master horizontal and vertical addresses are generated from a master synchronization signal along with write and read control signals. The data in the write register is read into the frame buffer memory at the slave horizontal and vertical addresses in response to the write control signal, and data in the frame buffer memory is read out from the master horizontal and vertical addresses in response to the read control signal, converted to analog signals, and combined to form a composite signal.
摘要翻译： 在电视系统中具有广泛适用性的帧同步器特别适用于色度时间压缩，亮度带宽降低的电视系统。 帧同步器将复合视频信号分离成其组成部分，从而使信号数字化所需的动态范围最小化，将色度信号解调为其正交分量并分离亮度信号。 复合视频信号中的同步信号产生从属分配信号和从属水平和垂直地址。 分离的色度正交分量和亮度信号被数字化，并且与从属分布信号和从属水平和垂直地址一起临时存储在提供独立缓冲的先进先出存储器中，从而适应高度 主从时间不匹配。 色度和亮度数据被累积在分配寄存器中，并被传送到向RAM缓冲存储器提供数据输入的写入寄存器。 主分配和主水平和垂直地址由主同步信号以及写和读控制信号产生。 写入寄存器中的数据响应于写入控制信号被读入到从属水平和垂直地址的帧缓冲存储器中，并且响应读取从主水平和垂直地址读出帧缓冲存储器中的数据 控制信号，转换为模拟信号，并组合形成复合信号。
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