Hybrid exposure for semiconductor devices
    2.
    发明授权
    Hybrid exposure for semiconductor devices 有权
    半导体器件的混合曝光

    公开(公告)号:US09543224B1

    公开(公告)日:2017-01-10

    申请号:US14964494

    申请日:2015-12-09

    摘要: Semiconductor packages and methods, systems, and apparatuses of forming such packages are described. A method of forming a semiconductor package may include encapsulating a semiconductor die with a molding compound, applying a seed layer on the die and the molding compound, applying a resist layer on the seed layer, exposing a first portion of the resist layer, and exposing a second portion of the resist layer. The first portion can include a first area of the resist layer to be used for forming a redistribution layer (RDL) without including a second area of the resist layer to be used for forming an electrical communications pathway between at least one of the contact pads and the RDL. The second portion can include the second area of the resist layer that includes the electrical communications pathway.

    摘要翻译: 描述了形成这种封装的半导体封装和方法,系统和装置。 形成半导体封装的方法可以包括用模塑料包封半导体管芯,在晶粒上施加种子层和模塑料,在种子层上施加抗蚀剂层,暴露抗蚀剂层的第一部分,并暴露 抗蚀剂层的第二部分。 第一部分可以包括用于形成再分布层(RDL)的抗蚀剂层的第一区域,而不包括用于在至少一个接触焊盘和至少一个接触焊盘之间形成电通信路径的抗蚀剂层的第二区域 RDL。 第二部分可以包括包括电通信路径的抗蚀剂层的第二区域。

    Copper interconnect structure and its formation
    5.
    发明授权
    Copper interconnect structure and its formation 有权
    铜互连结构及其形成

    公开(公告)号:US08969197B2

    公开(公告)日:2015-03-03

    申请号:US13475526

    申请日:2012-05-18

    IPC分类号: H01L21/44

    摘要: A structure with improved electromigration resistance and methods for making the same. A structure having improved electromigration resistance includes a bulk interconnect having a dual layer cap and a dielectric capping layer. The dual layer cap includes a bottom metallic portion and a top metal oxide portion. Preferably the metal oxide portion is MnO or MnSiO and the metallic portion is Mn or CuMn. The structure is created by doping the interconnect with an impurity (Mn in the preferred embodiment), and then creating lattice defects at a top portion of the interconnect. The defects drive increased impurity migration to the top surface of the interconnect. When the dielectric capping layer is formed, a portion reacts with the segregated impurities, thus forming the dual layer cap on the interconnect. Lattice defects at the Cu surface can be created by plasma treatment, ion implantation, a compressive film, or other means.

    摘要翻译: 具有改进的电迁移阻力的结构及其制造方法。 具有改进的电迁移电阻的结构包括具有双层盖和介电覆盖层的体互连。 双层帽包括底部金属部分和顶部金属氧化物部分。 优选地,金属氧化物部分是MnO或MnSiO,金属部分是Mn或CuMn。 通过用杂质(在优选实施例中为Mn)掺杂互连,然后在互连的顶部处产生晶格缺陷来产生该结构。 这些缺陷驱使增加的杂质向互连顶表面迁移。 当形成电介质盖层时,一部分与分离的杂质反应,从而在互连上形成双层盖。 Cu表面的晶格缺陷可以通过等离子体处理,离子注入,压缩薄膜或其他方式产生。