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1.发明授权
公开(公告)号：US4894115A
公开(公告)日：1990-01-16
申请号：US310149
申请日：1989-02-14
IPC分类号： B23K26/00 , B23K26/38 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/768 , H01L23/522 , H01L23/538 , H01L27/01 , H01S3/00 , H05K3/00
CPC分类号： H05K3/0035 , H01L21/31127 , H01L21/76804 , H01L2224/82039 , H05K2201/09827 , H05K2203/0165 , H05K2203/0207 , H05K2203/095 , H05K3/0008 , H05K3/0041 , H05K3/0055
摘要： The surface of a polymer dielectric layer is scanned repeatedly with a high energy continuous wave laser in a pattern to create via holes of desired size, shape and depth. This is followed by a short plasma etch. The via holes are produced at commercial production rates under direct computer control without use of masks and without damage to conductor material underlying the dielectric layer. A two-step technique usable to form a large hole to a partial depth in the dielectric layer and several smaller diameter holes within the large hole through the remainder of the dielectric layer depth allows formation of a large number of holes in a given area of a thick dielectric layer.
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2.发明授权Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer 失效使用可拆卸覆盖层测试电子电路和集成电路芯片的方法和配置
公开(公告)号：US4937203A
公开(公告)日：1990-06-26
申请号：US414895
申请日：1989-09-29
IPC分类号： G01R1/04 , G01R31/317 , H01L23/538
CPC分类号： G01R31/31723 , H01L23/5385 , H01L23/5387 , H01L23/5389 , G01R1/0408 , H01L2224/82039 , H01L2924/01014 , H01L2924/01322 , H01L2924/09701
摘要： The utilization of a removable overlay layer together with its associated metallization pattern, is used to effectively provide wafer scale integration for integrated circuit chips. The method and configuration of the present invention provide for the fabrication and testing of systems which are otherwise untestable. The present invention also permits integrated circuit systems to be tested in their final configuration in terms of speed and operating environment and the invention eliminates many of the problems associated with wafer or chip probes. The present invention also utilizes special test chips which are either temporarily or permanently affixed in an integrated circuit chip package.
摘要翻译： 使用可移除覆盖层及其相关联的金属化图案用于有效地为集成电路芯片提供晶片级整合。 本发明的方法和结构提供了另外不可测试的系统的制造和测试。 本发明还允许集成电路系统在速度和操作环境方面以其最终配置进行测试，并且本发明消除了与晶片或芯片探针相关的许多问题。 本发明还使用临时或永久地固定在集成电路芯片封装中的专用测试芯片。
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3.发明授权Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer 失效使用可拆卸覆盖层测试电子电路和集成电路芯片的方法和配置
公开(公告)号：US4884122A
公开(公告)日：1989-11-28
申请号：US230654
申请日：1988-08-05
IPC分类号： G01R31/317 , H01L23/538
CPC分类号： H01L23/5389 , G01R31/31723 , H01L23/5385 , H01L23/5387 , H01L2224/82039 , H01L2924/01322
摘要： The utilization of a removable overlay layer together with its associated metalization pattern, is used to effectively provide wafer scale integration for integrated circuit chips. The method and configuration of the present invention provide for the fabrication and testing of systems which are otherwise untestable. The present invention also permits integrated circuit systems to be tested in their final configuration in terms of speed and operating environment and the invention eliminates many of the problems associated with wafer or chip probes. The present invention also utilizes special test chips which are either temporarily or permanently affixed in an integrated circuit chip package.
摘要翻译： 可移除覆盖层及其相关联的金属化图案的利用被用于有效地为集成电路芯片提供晶片级整合。 本发明的方法和结构提供了另外不可测试的系统的制造和测试。 本发明还允许集成电路系统在速度和操作环境方面以其最终配置进行测试，并且本发明消除了与晶片或芯片探针相关的许多问题。 本发明还使用临时或永久地固定在集成电路芯片封装中的专用测试芯片。
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4.发明授权Integrated circuit packaging configuration for rapid customized design and unique test capability 失效集成电路封装配置，快速定制设计和独特的测试能力
公开(公告)号：US4866508A
公开(公告)日：1989-09-12
申请号：US912457
申请日：1986-09-26
IPC分类号： H01L25/18 , G01R31/3185 , H01L23/538 , H01L25/04
CPC分类号： G01R31/318505 , H01L23/5382 , H01L2924/0002 , Y10T29/4913
摘要： The present invention employs a high density interconnect method to take advantage of a packaging arrangement in which full customization of an integrated circuit chip package is providable in a single metallization layer. The integrated circuit chips are positioned to take full advantage of a wiring layer which includes a plurality of periodically interrupted conductor patterns. All of the customization is provided in a single layer which may be readily fabricated and produced in a single day making it possible for extremely rapid turn around time in the design of complex integrated circuit systems, particularly those constructed from readily available integrated circuit components including microprocessors, random access memory chips, decoders and the like. An integrated circuit is also disclosed for fully taking advantage of the capabilities of testing made available by the high density interconnect system.
摘要翻译： 本发明采用高密度互连方法来利用其中集成电路芯片封装的完全定制在单个金属化层中提供的封装结构。 定位集成电路芯片以充分利用包括多个周期性中断的导体图案的布线层。 所有的定制都提供在单层中，这可以在一天内容易地制造和制造，使得在复杂的集成电路系统的设计中特别是由容易获得的集成电路组件（包括微处理器 ，随机存取存储器芯片，解码器等。 还公开了一种用于充分利用由高密度互连系统可用的测试能力的集成电路。
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5.发明授权Apparatus for packaging integrated circuit chips employing a polymer film overlay layer 失效用于封装采用聚合物膜覆盖层的集成电路芯片的装置
公开(公告)号：US5094709A
公开(公告)日：1992-03-10
申请号：US516895
申请日：1990-04-26
IPC分类号： H01L21/00 , H01L21/56 , H01L21/58 , H01L23/31 , H01L23/538
CPC分类号： H01L24/27 , H01L21/56 , H01L21/67121 , H01L23/3164 , H01L23/5389 , H01L24/75 , H01L24/83 , H01L2224/2919 , H01L2224/75315 , H01L2224/8319 , H01L2224/8385 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01077 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/14
摘要： A method and apparatus are provided for disposing a polymer film on an irregularly-shaped substrate at relatively high temperatures. In particular, the method and apparatus of the present invention provide a system for the packaging of very large scale integrated circuit chips. The system of the present invention particularly solves problems associated with high temperature processing and problems associated with the highly irregular surfaces that result. Nonetheless, the resultant product is capable of being fashioned into circuit chip systems which are independently testable and which may be reconfigured after testing by removal of the polymer film itself.
摘要翻译： 提供了一种用于在较高温度下将聚合物膜设置在不规则形状的基底上的方法和装置。 特别地，本发明的方法和装置提供了一种用于包装非常大规模集成电路芯片的系统。 本发明的系统特别地解决了与高温处理相关的问题和与导致的高度不规则的表面有关的问题。 然而，所得产品能够被制成可独立测试的电路芯片系统，并且可以在通过去除聚合物膜本身进行测试之后重新配置。
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6.发明授权Method for packaging integrated circuit chips employing a polymer film overlay layer 失效使用聚合物膜覆盖层封装集成电路芯片的方法
公开(公告)号：US4933042A
公开(公告)日：1990-06-12
申请号：US240367
申请日：1988-08-30
IPC分类号： H01L21/00 , H01L21/56 , H01L21/58 , H01L23/31 , H01L23/538
CPC分类号： H01L24/83 , H01L21/56 , H01L21/67121 , H01L23/3164 , H01L23/5389 , H01L24/75 , H01L2224/2919 , H01L2224/75315 , H01L2224/8319 , H01L2224/8385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0665 , H01L2924/07802 , H01L2924/12042 , H01L2924/14 , Y10T156/1092
摘要： A method and apparatus are provided for disposing a polymer film on an irregularly-shaped substrate at relatively high temperatures. In particular, the method and apparatus of the present invention provide a system for the packaging of very large scale intergrated circuit chips. The system of the present invention particularly solves problems associated with high temperature processing and problems associated with the highly irregular surfaces that result. Nonetheless, the resultant product is capable of being fashioned into circuit chip systems which are independently testable and which may be reconfigured after testing by removal of the polymer film itself.
摘要翻译： 提供了一种用于在较高温度下将聚合物膜设置在不规则形状的基底上的方法和装置。 特别地，本发明的方法和装置提供了一种用于包装非常大规模的集成电路芯片的系统。 本发明的系统特别地解决了与高温处理相关的问题和与导致的高度不规则的表面有关的问题。 然而，所得产品能够被制成可独立测试的电路芯片系统，并且可以在通过去除聚合物膜本身进行测试之后重新配置。
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公开(公告)号：US4835704A
公开(公告)日：1989-05-30
申请号：US947461
申请日：1986-12-29
IPC分类号： G03F1/00 , G03F1/08 , G03F7/20 , H01L21/00 , H01L21/027 , H01L21/30 , H01L21/3213 , H01L21/60 , H01L21/768 , H01L21/82 , H01L23/538 , H05K3/00
CPC分类号： H01L24/25 , G03F7/704 , H01L21/6715 , H01L21/768 , H01L23/5389 , H01L24/24 , H01L24/75 , H01L24/76 , H01L2224/18 , H01L2224/75 , H01L2224/75753 , H01L2224/758 , H01L2224/759 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/12042 , H01L2924/12043 , H01L2924/14 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , Y10S148/093 , Y10S430/146
摘要： An adaptive method and system are disclosed for providing high density interconnections of very large scale integrated circuits on a substrate. The procedure is performed in four basic steps: first an artwork representation for the interconnections of the integrated circuits is generated. This artwork representation is stored in a computer data base and assumes the integrated circuits to be at predetermined ideal locations and positions on the substrate. Second, using imaging, the actual positions of each integrated circuit on the substrate are determined. The actual positions of the integrated circuits are compared with their ideal positions to compute an offset and rotation for each integrated circuit on the substrate. Third, the computed offsets and rotations are then used to modify the artwork representation stored in the data base to account for the actual locations and positions of the integrated circuits on the substrate. Finally, the modified artwork representation is used to drive a direct writing laser lithography system that actually forms the high density interconnections of the integrated circuits on the substrate. The artwork representations are stored in computer data bases in vector form to minimize storage requirements. The laser beam produced by the lithography system is raster scanned on the substrate. Modulation of the laser beam is controlled by the real time conversion of the vector representation of the modified artwork to be a bit mapped representation. To assure accurate formations of the interconnects, a feedback alignment system is used to accurately position the laser beam throughout its raster scan.
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8.发明授权Television frame synchronizer with independently controllable input/output rates 失效电视帧同步器具有可独立控制的输入/输出速率
公开(公告)号：US4646151A
公开(公告)日：1987-02-24
申请号：US697601
申请日：1985-02-01
CPC分类号： H04N5/0736
摘要： A frame synchronizer having broad applicability in television systems is particularly adapted for use in a chrominance time-compressed, luminance bandwidth reduced television system. The frame synchronizer, which separates the composite video signal into its component parts and thereby minimizes the dynamic range required to digitize the signal, demodulates the chrominance signal into its quadrature components and separates the luminance signal. The synchronization signal in the composite video signal generates slave distribution signals and slave horizontal and vertical addresses. The separated chrominance quadrature components and the luminance signal are digitized and, along with the slave distribution signals and the slave horizontal and vertical addresses, are temporarily stored in first-in, first-out memories which provide independent buffering and thereby accommodate a high degree of mismatch between master and slave timing. The chrominance and luminance data are accumulated in distribution registers and transferred to write registers which provide the data input to a frame buffer memory. Master distribution and master horizontal and vertical addresses are generated from a master synchronization signal along with write and read control signals. The data in the write register is read into the frame buffer memory at the slave horizontal and vertical addresses in response to the write control signal, and data in the frame buffer memory is read out from the master horizontal and vertical addresses in response to the read control signal, converted to analog signals, and combined to form a composite signal.
摘要翻译： 在电视系统中具有广泛适用性的帧同步器特别适用于色度时间压缩，亮度带宽降低的电视系统。 帧同步器将复合视频信号分离成其组成部分，从而使信号数字化所需的动态范围最小化，将色度信号解调为其正交分量并分离亮度信号。 复合视频信号中的同步信号产生从属分配信号和从属水平和垂直地址。 分离的色度正交分量和亮度信号被数字化，并且与从属分布信号和从属水平和垂直地址一起临时存储在提供独立缓冲的先进先出存储器中，从而适应高度 主从时间不匹配。 色度和亮度数据被累积在分配寄存器中，并被传送到向RAM缓冲存储器提供数据输入的写入寄存器。 主分配和主水平和垂直地址由主同步信号以及写和读控制信号产生。 写入寄存器中的数据响应于写入控制信号被读入到从属水平和垂直地址的帧缓冲存储器中，并且响应读取从主水平和垂直地址读出帧缓冲存储器中的数据 控制信号，转换为模拟信号，并组合形成复合信号。
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9.发明授权Integrated circuit packaging configuration for rapid customized design and unique test capability 失效集成电路封装配置，快速定制设计和独特的测试能力
公开(公告)号：US5214655A
公开(公告)日：1993-05-25
申请号：US784094
申请日：1991-10-28
IPC分类号： G01R31/3185 , H01L23/538
CPC分类号： H01L23/5382 , G01R31/318505 , H01L2924/0002 , H01L2924/3011
摘要： A packaged electronics system, having respective portions each with respective input and output ports, and having interconnection busses between certain of these ports, is tested as follows. Each input port has a set of first transmission gates associated therewith for selectively disconnecting it during testing from the end of each interconnection bus connected bit during normal operation. Each input port has a second set of transmission gates associated therewith for selectively applying test vectors thereto during testing as provided in parallel form from a serially loaded shift register. Each output port connects to the input connections of a respective set of tristate drivers for selectively applying its output signals at relatively low source impedance to at least one interconnection bus connected from the output connections of that set of tristate drivers. A shift register converts the signals appearing in parallel at least one end of each interconnection bus to a concatenation of test results in serial form.
摘要翻译： 具有相应部分的封装电子系统各自具有相应的输入和输出端口，并且在这些端口中的某些端口之间具有互连总线，如下进行测试。 每个输入端口具有与其相关联的一组第一传输门，用于在正常操作期间从每个互连总线连接的位的端部进行测试时选择性地断开它。 每个输入端口具有与之相关联的第二组传输门，用于在测试期间选择性地将测试向量应用于串行装载的移位寄存器的并行形式。 每个输出端口连接到相应组的三态驱动器的输入连接，用于选择性地将其输出信号以相对低的源阻抗施加到从该组三态驱动器的输出连接连接的至少一个互连总线。 移位寄存器将并联出现的每个互连总线的至少一端的信号以串行形式连接到测试结果。
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公开(公告)号：US5359496A
公开(公告)日：1994-10-25
申请号：US67157
申请日：1993-05-26
IPC分类号： H01L23/02 , H01L21/58 , H01L23/04 , H01L23/10 , H01L23/538 , H01L23/552 , H01L25/065 , H05K1/11
CPC分类号： H01L24/83 , H01L23/04 , H01L23/10 , H01L23/5383 , H01L23/5389 , H01L23/552 , H01L24/24 , H01L24/29 , H01L24/82 , H01L25/0655 , H01L2224/24137 , H01L2224/24225 , H01L2224/24227 , H01L2224/2919 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73267 , H01L2224/82039 , H01L2224/8319 , H01L2224/8385 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15787 , H01L2924/16152 , H01L2924/3025
摘要： A body is hermetically sealed by electroplating a hermetic layer over the exterior surface of the body. A hermetic high density interconnect structure is provided by forming a continuous metal layer over the outermost dielectric layer of the multilayer interconnect structure and by disposing that continuous metal layer in a hermetically sealing relation to the substrate of the high density interconnect structure. A variety of techniques may be used for providing electrical feedthroughs between the interior and exterior of the hermetic enclosure as may a pseudo-hermetic enclosure in those situations where true hermeticity is not required.
摘要翻译： 通过在身体的外表面上电镀一层密封层，使身体密封。 通过在多层互连结构的最外层电介质层上形成连续的金属层，并通过将该连续金属层与高密度互连结构的衬底密封地设置，来提供密封的高密度互连结构。 可以使用各种技术来在密封外壳的内部和外部之间提供电馈通，如在不需要真实气密的那些情况下的伪密封封壳。
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