公开(公告)号：US5345365A

公开(公告)日：1994-09-06

申请号：US878495

申请日：1992-05-05

申请人： Terry O. Herndon ,  Jack I. Raffel

发明人： Terry O. Herndon ,  Jack I. Raffel

IPC分类号： H01L23/48 ,  H01L23/498 ,  H01L25/18 ,  H05K3/30 ,  H05K3/32 ,  H05K3/40 ,  H05K7/02

CPC分类号： H01L23/49816 ,  H01L23/49811 ,  H01L24/72 ,  H01L25/18 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K3/303 ,  H05K3/326 ,  H05K3/4007

摘要： An interconnection system for high performance electronic hybrids employs micro-machined features on a substrate to connect directly to miniature electronic components, such as integrated circuits. The micro-machined features may include posts for connecting to bonding pads of standard components and may also include rails for alignment of components and connections to specially made components.

摘要翻译： 用于高性能电子混合器的互连系统在基板上使用微加工特征直接连接到微型电子部件，例如集成电路。 微加工的特征可以包括用于连接到标准部件的接合焊盘的柱，并且还可以包括用于将组件对准的轨道和与特定构件的连接。

公开(公告)号：US4585490A

公开(公告)日：1986-04-29

申请号：US657128

申请日：1984-10-03

申请人： Jack I. Raffel ,  John A. Yasaitis ,  Glenn H. Chapman ,  Mark L. Naiman

发明人： Jack I. Raffel ,  John A. Yasaitis ,  Glenn H. Chapman ,  Mark L. Naiman

IPC分类号： H01L21/268 ,  H01L21/768 ,  H01L21/265

CPC分类号： H01L21/268 ,  H01L21/76894 ,  Y10S438/94

摘要： An integrated circuit device including a link point for electrically connecting a plurality of metal layers, comprising a first metal layer, a link insulating layer, a second metal layer and diffusion barrier layers between the link insulator layer and each of the first metal layer and the second metal layer. The metal layers are connected by exposing the link point to a low-power laser for a relatively long pulse width.

摘要翻译： 一种集成电路装置，包括用于电连接多个金属层的连接点，包括第一金属层，链路绝缘层，第二金属层和在所述链路绝缘体层与第一金属层和第一金属层中的每一个之间的扩散阻挡层 第二金属层。 金属层通过将连接点暴露于相对长的脉冲宽度的低功率激光器来连接。

公开(公告)号：US4184172A

公开(公告)日：1980-01-15

申请号：US773637

申请日：1977-02-28

申请人： Jack I. Raffel ,  Stephen E. Bernacki

发明人： Jack I. Raffel ,  Stephen E. Bernacki

IPC分类号： H01L21/76 ,  H01L27/04

CPC分类号： H01L21/76

摘要： A process is described which combines polycrystalline isolation of collectors and shallow oxide isolation of bases. This approach is capable of providing deep dielectric isolation, surface planarity and the high density of walled emitter geometries, a combination heretofore unobtainable by any other means.This isolation scheme has been used to fabricate ECL gate chains. The transistors were located in 2.5 micron thick n-epi islands surrounded by 5.times.10.sup.5 ohm-cm polysilicon selectively oxidized with silicon nitride masking to a thickness of one micron. The oxide "bump" at the nitride mask was typically 3000 A and the epi-poly step height was as small as 2600 A. The circuits have polysilicon resistors and were fabricated using both thermal diffusion and ion implantation. The power-delay product of these circuits was approximately one-half that of junction isolated circuits.

摘要翻译： 描述了结合收集器的多晶分离和碱的浅氧化物隔离的方法。 这种方法能够提供深的介电隔离，表面平面性和高密度的壁发射器几何形状，这是迄今为止通过任何其他方式无法获得的组合。 该隔离方案已被用于制造ECL门链。 晶体管位于由氮化硅选择性氧化的5×10 5欧姆 - 厘米多晶硅所围绕的2.5微米厚的n外延岛中，其掩盖厚度为1微米。 氮化物掩模上的氧化物“凸块”通常为3000A，外延多层台阶高度为2600A。电路具有多晶硅电阻器，并使用热扩散和离子注入制造。 这些电路的功率延迟产物大约是结隔离电路的一半。

公开(公告)号：US4127900A

公开(公告)日：1978-11-28

申请号：US808068

申请日：1977-06-20

申请人： Jack I. Raffel ,  John A. Yasaitis

发明人： Jack I. Raffel ,  John A. Yasaitis

IPC分类号： G11C11/401 ,  G11C16/04 ,  H01L21/306 ,  H01L21/761 ,  H01L21/764 ,  H01L21/822 ,  H01L23/52 ,  H01L27/10 ,  G11C7/00 ,  G11C11/24

CPC分类号： H01L27/101 ,  G11C16/0466 ,  H01L21/30608 ,  H01L21/761 ,  H01L21/764 ,  H01L21/822 ,  H01L23/52 ,  H01L2924/0002 ,  H01L2924/3011

摘要： An improved method for reading metal dual insulator semiconductor capacitor memories is disclosed. The memory contains a plurality of capacitor cells, each cell comprising a semiconductor substrate layer and a high conductivity layer sandwiching two insulator layers. The substrate is doped to provide avalanche breakdown in a surface depletion layer at a voltage comparable to the write voltage in the accumulation direction. According to the invention, a small variable voltage is applied across a selected cell or cells. The range of voltage includes a "flat-band" portion of the hysteresis loop describing the voltage-capacitance relationship for the capacitor memory. The unselected cells are maintained in a depletion state in which their capacitance is a minimum. A change or the absence of a change in the current through the capacitor indicates the state of the capacitor cell.

摘要翻译： 公开了一种用于读取金属双绝缘体半导体电容器存储器的改进方法。 存储器包含多个电容器单元，每个单元包括半导体衬底层和夹着两个绝缘体层的高电导率层。 掺杂衬底以在表面耗尽层中以与积累方向上的写入电压相当的电压提供雪崩击穿。 根据本发明，在所选择的单元或单元上施加小的可变电压。 电压范围包括描述电容器存储器的电压 - 电容关系的磁滞回线的“平带”部分。 未选择的电池保持在其电容最小的耗尽状态。 通过电容器的电流的改变或不存在改变电容器电池的状态。