公开(公告)号：US06821913B2

公开(公告)日：2004-11-23

申请号：US10232260

申请日：2002-08-29

Applicant: Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Cheng-Tsung Ni

Inventor： Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Cheng-Tsung Ni

IPC: H01L2131

CPC classification number: H01L29/66734 ,  H01L21/0274 ,  H01L21/76224 ,  H01L29/42368

Abstract: Embodiments of the present invention are directed to an improved method for forming dual oxide layers at the bottom of a trench of a substrate. A substrate has a trench which includes a bottom and a sidewall. The trench may be created by forming a mask oxide layer on the substrate; defining the mask oxide layer to form a patterned mask oxide layer and exposing a partial surface of the substrate to form a window; and using the patterned mask oxide layer as an etching mask to form the trench in the window. A first oxide layer is formed on the sidewall and the bottom of the trench of the substrate. A photoresist layer is formed on the substrate, filling the trench of the substrate. The method further comprises partially etching back the photoresist layer to leave a remaining photoresist layer in the trench. The height of the remaining photoresist layer is lower than the depth of the trench. A curing treatment of the remaining photoresist layer is performed after the partial etching. The patterned mask oxide layer and a portion of the first oxide layer are removed to leave a remaining first oxide layer at the bottom of the trench. The remaining photoresist layer is removed. A second oxide layer is formed on the substrate covering at least the remaining first oxide layer to form the dual oxide layers at the bottom of the trench.

Abstract translation: 本发明的实施例涉及一种用于在衬底的沟槽的底部形成双重氧化物层的改进方法。 衬底具有包括底部和侧壁的沟槽。 可以通过在衬底上形成掩模氧化物层来形成沟槽; 限定所述掩模氧化物层以形成图案化掩模氧化物层并暴露所述衬底的部分表面以形成窗口; 并且使用图案化的掩模氧化物层作为蚀刻掩模以在窗口中形成沟槽。 第一氧化物层形成在衬底的沟槽的侧壁和底部上。 在衬底上形成光刻胶层，填充衬底的沟槽。 该方法还包括部分地蚀刻光致抗蚀剂层以在沟槽中留下残留的光致抗蚀剂层。 剩余的光致抗蚀剂层的高度低于沟槽的深度。 在部分蚀刻之后进行剩余光致抗蚀剂层的固化处理。 图案化的掩模氧化物层和第一氧化物层的一部分被去除以在沟槽的底部留下剩余的第一氧化物层。 去除剩余的光致抗蚀剂层。 在衬底上形成第二氧化物层，至少覆盖剩余的第一氧化物层，以在沟槽的底部形成双氧化层。

公开(公告)号：US08912621B1

公开(公告)日：2014-12-16

申请号：US13546867

申请日：2012-07-11

Applicant: Chiao-Shun Chuang ,  Kai-Yu Chen ,  Cheng-Chin Huang

Inventor： Chiao-Shun Chuang ,  Kai-Yu Chen ,  Cheng-Chin Huang

IPC: H01L29/47

CPC classification number: H01L29/872 ,  H01L29/66143

Abstract: During fabrication of a semiconductor device, a width of semiconductor mesas between isolation trenches in the semiconductor device is varied in different regions. In particular, the width of the mesas is smaller in a termination region of the semiconductor device than in a cell or active region. When an oxide layer is subsequently grown, the semiconductor mesas between the trenches in the termination region are at least partially consumed so that the semiconductor mesas in the cell region and the termination region have different heights. Therefore, a contact photomask is not needed to isolate the semiconductor mesas in the termination region. Furthermore, after a planarization operation (such as chemical mechanical polishing), the semiconductor device may have a planar top surface than if contact holes are created. This may allow the metal layer deposited on top of the cell region and the termination region to be flat.

Abstract translation: 在制造半导体器件期间，半导体器件中的隔离沟槽之间的半导体台面的宽度在不同的区域中变化。 特别地，在半导体器件的端接区域中，台面的宽度小于单元或有源区域中的宽度。 当随后生长氧化物层时，终止区域中的沟槽之间的半导体台面至少部分消耗，使得单元区域和端接区域中的半导体台面具有不同的高度。 因此，不需要接触光掩模来隔离终端区域中的半导体台面。 此外，在平面化操作（例如化学机械抛光）之后，半导体器件可以具有比产生接触孔的平坦的顶表面。 这可以使沉积在电池区域和终端区域顶部的金属层变平坦。

公开(公告)号：US08314471B2

公开(公告)日：2012-11-20

申请号：US12620473

申请日：2009-11-17

Applicant: Chiao-Shun Chuang ,  Tony Huang

Inventor： Chiao-Shun Chuang ,  Tony Huang

IPC: H01L29/02

CPC classification number: H01L29/7813 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, the present invention includes a semiconductor power device. The semiconductor power device comprises a trenched gate and a trenched field region. The trenched gate is disposed vertically within a trench in a semiconductor substrate. The trenched field region is disposed vertically within the trench and below the trenched gate. A lower portion of the trenched field region tapers to disperse an electric field.

Abstract translation: 在一个实施例中，本发明包括半导体功率器件。 半导体功率器件包括沟槽栅极和沟槽场区域。 沟槽栅极垂直设置在半导体衬底的沟槽内。 沟槽场区域垂直设置在沟槽内并且在沟槽栅极下方。 沟槽场区域的下部逐渐变细以分散电场。

公开(公告)号：US07084457B2

公开(公告)日：2006-08-01

申请号：US10774212

申请日：2004-02-05

Applicant: Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng

Inventor： Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng

IPC: H01L29/76 ,  H01L31/062

CPC classification number: H01L29/7811 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7813

Abstract: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.

Abstract translation: 引入了具有沟槽总线结构的DMOS器件。 沟槽总线结构包括形成在P基板上的场氧化物层和从场氧化物层的顶表面向下延伸到P衬底的下部的沟槽。 形成栅极氧化层和多晶硅母线，以填充沟槽作为总线结构的主要部分。 此外，在多晶硅总线和场氧化物层的顶部形成隔离层和金属线。 在隔离层中形成开口以形成多晶硅母线和金属线之间的连接。 在具体实施例中，同时形成DMOS器件的总线沟槽和栅极沟槽，同时形成多晶硅母线和栅电极。 因此，总线结构能够形成DMOS晶体管，而不需要用于定义多晶硅总线位置的任何光刻步骤。

公开(公告)号：US20130099310A1

公开(公告)日：2013-04-25

申请号：US13710816

申请日：2012-12-11

Applicant: Chiao-Shun Chuang

Inventor： Chiao-Shun Chuang

IPC: H01L29/78

CPC classification number: H01L29/7827 ,  H01L27/0727 ,  H01L29/7806

Abstract: In one embodiment the present invention includes a semiconductor device. The semiconductor device comprises a first semiconductor region, a second semiconductor region and a trench region. The first semiconductor region is of a first conductivity type and a first conductivity concentration. The trench region includes a metal layer in contact with the first semiconductor region to form a metal-semiconductor junction. The second semiconductor region is adjacent to the first semiconductor region that has a second conductivity type and a second conductivity concentration. The second semiconductor region forms a PN junction with the first semiconductor region, and the trench region has a depth such that the metal-semiconductor junction is proximate to the PN junction.

Abstract translation: 在一个实施例中，本发明包括半导体器件。 半导体器件包括第一半导体区域，第二半导体区域和沟槽区域。 第一半导体区域是第一导电类型和第一电导率浓度。 沟槽区域包括与第一半导体区域接触以形成金属 - 半导体结的金属层。 第二半导体区域与具有第二导电类型和第二电导率浓度的第一半导体区域相邻。 第二半导体区域与第一半导体区域形成PN结，并且沟槽区域具有使得金属 - 半导体结接近PN结的深度。

公开(公告)号：US07265024B2

公开(公告)日：2007-09-04

申请号：US11329870

申请日：2006-01-10

Applicant: Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng

Inventor： Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng

IPC: H01L21/76 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/336 ,  H01L29/76

CPC classification number: H01L29/7811 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7813

Abstract: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.

Abstract translation: 引入了具有沟槽总线结构的DMOS器件。 沟槽总线结构包括形成在P基板上的场氧化物层和从场氧化物层的顶表面向下延伸到P衬底的下部的沟槽。 形成栅极氧化层和多晶硅母线，以填充沟槽作为总线结构的主要部分。 此外，在多晶硅总线和场氧化物层的顶部形成隔离层和金属线。 在隔离层中形成开口以形成多晶硅母线和金属线之间的连接。 在具体实施例中，同时形成DMOS器件的总线沟槽和栅极沟槽，同时形成多晶硅母线和栅电极。 因此，总线结构能够形成DMOS晶体管，而不需要用于定义多晶硅总线位置的任何光刻步骤。

公开(公告)号：US06998315B2

公开(公告)日：2006-02-14

申请号：US11056450

申请日：2005-02-11

Applicant: Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

Inventor： Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/0661 ,  H01L29/41766 ,  H01L29/7802

Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench. A metal layer covers portions of the passivation layer on the side walls of the trench to expose a part of the passivation layer over the bottom surface of the trench.

Abstract translation: 本发明的实施例涉及一种为沟槽DMOS器件提供的终端结构，以减少由于在有源区域的边界处的电场拥挤而产生的电流泄漏及其制造方法。 在一个实施例中，沟槽DMOS器件的端接结构包括在衬底上的第一类型导电性衬底和第一类型导电性的外延层。 外延层具有比衬底更低的掺杂浓度。 在外延层内提供第二类导电体的主体区域。 沟槽延伸穿过衬底的有源区域和边缘之间的主体区域。 栅极氧化物层排列沟槽并且延伸到沟槽和有源区域之间的主体区域的上表面。 钝化层形成在栅极氧化层上，包括沟槽的侧壁和底表面。 金属层覆盖沟槽侧壁上的钝化层的部分，以使钝化层的一部分暴露在沟槽的底表面上。

公开(公告)号：US06855986B2

公开(公告)日：2005-02-15

申请号：US10652442

申请日：2003-08-28

Applicant: Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

Inventor： Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/772

CPC classification number: H01L29/7813 ,  H01L29/0661 ,  H01L29/41766 ,  H01L29/7802

Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench. A metal layer covers portions of the passivation layer on the side walls of the trench to expose a part of the passivation layer over the bottom surface of the trench.

Abstract translation: 本发明的实施例涉及一种为沟槽DMOS器件提供的终端结构，以减少由于在有源区域的边界处的电场拥挤而产生的电流泄漏及其制造方法。 在一个实施例中，沟槽DMOS器件的端接结构包括在衬底上的第一类型导电性衬底和第一类型导电性的外延层。 外延层具有比衬底更低的掺杂浓度。 在外延层内提供第二类导电体的主体区域。 沟槽延伸穿过衬底的有源区域和边缘之间的主体区域。 栅极氧化物层排列沟槽并且延伸到沟槽和有源区域之间的主体区域的上表面。 钝化层形成在栅极氧化层上，包括沟槽的侧壁和底表面。 金属层覆盖沟槽侧壁上的钝化层的部分，以使钝化层的一部分暴露在沟槽的底表面上。

公开(公告)号：US20140054683A1

公开(公告)日：2014-02-27

申请号：US13646906

申请日：2012-10-08

Applicant: Chiao-Shun Chuang ,  Tony Huang

Inventor： Chiao-Shun Chuang ,  Tony Huang

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, the present invention includes a semiconductor power device. The semiconductor power device comprises a trenched gate and a trenched field region. The trenched gate is disposed vertically within a trench in a semiconductor substrate. The trenched field, region is disposed vertically within the trench and below the trenched gate. A lower portion of the trenched field region tapers to dispose an electric field.

Abstract translation: 在一个实施例中，本发明包括半导体功率器件。 半导体功率器件包括沟槽栅极和沟槽场区域。 沟槽栅极垂直设置在半导体衬底的沟槽内。 沟槽场区域垂直设置在沟槽内并在沟槽栅极下方。 沟槽场区域的下部逐渐变细以设置电场。

公开(公告)号：US20110133271A1

公开(公告)日：2011-06-09

申请号：US12630088

申请日：2009-12-03

Applicant: Chiao-Shun Chuang

Inventor： Chiao-Shun Chuang

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L29/7827 ,  H01L27/0727

Abstract: In one embodiment the present invention includes a semiconductor device. The semiconductor device comprises a first semiconductor region, a second semiconductor region and a trench region. The first semiconductor region is of a first conductivity type and a first conductivity concentration. The trench region includes a metal layer in contact with the first semiconductor region to form a metal-semiconductor junction. The second semiconductor region is adjacent to the first semiconductor region that has a second conductivity type and a second conductivity concentration. The second semiconductor region forms a PN junction with the first semiconductor region, and the trench region has a depth such that the metal-semiconductor junction is proximate to the PN junction.

Abstract translation: 在一个实施例中，本发明包括半导体器件。 半导体器件包括第一半导体区域，第二半导体区域和沟槽区域。 第一半导体区域是第一导电类型和第一电导率浓度。 沟槽区域包括与第一半导体区域接触以形成金属 - 半导体结的金属层。 第二半导体区域与具有第二导电类型和第二电导率浓度的第一半导体区域相邻。 第二半导体区域与第一半导体区域形成PN结，并且沟槽区域具有使得金属 - 半导体结接近PN结的深度。