公开(公告)号：US08912621B1

公开(公告)日：2014-12-16

申请号：US13546867

申请日：2012-07-11

Applicant: Chiao-Shun Chuang ,  Kai-Yu Chen ,  Cheng-Chin Huang

Inventor： Chiao-Shun Chuang ,  Kai-Yu Chen ,  Cheng-Chin Huang

IPC: H01L29/47

CPC classification number: H01L29/872 ,  H01L29/66143

Abstract: During fabrication of a semiconductor device, a width of semiconductor mesas between isolation trenches in the semiconductor device is varied in different regions. In particular, the width of the mesas is smaller in a termination region of the semiconductor device than in a cell or active region. When an oxide layer is subsequently grown, the semiconductor mesas between the trenches in the termination region are at least partially consumed so that the semiconductor mesas in the cell region and the termination region have different heights. Therefore, a contact photomask is not needed to isolate the semiconductor mesas in the termination region. Furthermore, after a planarization operation (such as chemical mechanical polishing), the semiconductor device may have a planar top surface than if contact holes are created. This may allow the metal layer deposited on top of the cell region and the termination region to be flat.

Abstract translation: 在制造半导体器件期间，半导体器件中的隔离沟槽之间的半导体台面的宽度在不同的区域中变化。 特别地，在半导体器件的端接区域中，台面的宽度小于单元或有源区域中的宽度。 当随后生长氧化物层时，终止区域中的沟槽之间的半导体台面至少部分消耗，使得单元区域和端接区域中的半导体台面具有不同的高度。 因此，不需要接触光掩模来隔离终端区域中的半导体台面。 此外，在平面化操作（例如化学机械抛光）之后，半导体器件可以具有比产生接触孔的平坦的顶表面。 这可以使沉积在电池区域和终端区域顶部的金属层变平坦。

公开(公告)号：US20070102697A1

公开(公告)日：2007-05-10

申请号：US11164092

申请日：2005-11-10

Applicant: Fang-Chung Chen ,  Chiao-Shun Chuang

Inventor： Fang-Chung Chen ,  Chiao-Shun Chuang

IPC: H01L29/08

CPC classification number: H01L51/105 ,  H01L51/057

Abstract: A junction structure of an organic semiconductor device including an organic semiconductor layer, a conductive layer and a modifying layer is provided. The modifying layer is formed between the organic semiconductor layer and the conductive layer, wherein the modifying layer includes an inorganic compound or an organic complex compound. An organic thin film transistor including a gate, a source/drain, a dielectric layer, an organic semiconductor layer and at least a modifying layer is also provided. The gate is electrically isolated from the source/drain. The dielectric layer is disposed between the gate and the source/drain. The organic semiconductor layer is disposed between the source and the drain. The modifying layer is disposed between the organic semiconductor layer and the source/drain, wherein the modifying layer includes an inorganic compound or an organic complex compound.

Abstract translation: 提供了包括有机半导体层，导电层和改性层的有机半导体器件的结结构。 在有机半导体层和导电层之间形成改性层，其中改性层包括无机化合物或有机络合物。 还提供了包括栅极，源极/漏极，电介质层，有机半导体层和至少改性层的有机薄膜晶体管。 栅极与源极/漏极电隔离。 电介质层设置在栅极和源极/漏极之间。 有机半导体层设置在源极和漏极之间。 改性层设置在有机半导体层和源极/漏极之间，其中改性层包括无机化合物或有机络合物。

公开(公告)号：US07087958B2

公开(公告)日：2006-08-08

申请号：US10771957

申请日：2004-02-03

Applicant: Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Hsing-Huang Hsieh

Inventor： Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Hsing-Huang Hsieh

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L29/7811 ,  H01L29/402 ,  H01L29/407 ,  H01L29/7813

Abstract: In one embodiment of the invention, a semiconductor device set includes at least one trench-typed MOSFET and a trench-typed termination structure. The trench-typed MOSFET has a trench profile and includes a gate oxide layer in the trench profile, and a polysilicon layer on the gate oxide layer. The trench-typed termination structure has a trench profile and includes an oxide layer in the trench profile. A termination polysilicon layer with discrete features separates the termination polysilicon layer. An isolation layer covers the termination polysilicon layer and filling the discrete features. The trench-typed MOSFET and the trench-typed termination structure may be formed on a DMOS device including an N+ silicon substrate, an N epitaxial layer on the N+ silicon substrate, and a P epitaxial layer on the N epitaxial layer. The trench profiles of the trench-typed MOSFET and of the trench-typed termination structure may penetrate through the P epitaxial layer into the N epitaxial layer.

Abstract translation: 在本发明的一个实施例中，半导体器件组包括至少一个沟槽型MOSFET和沟槽型端接结构。 沟槽型MOSFET具有沟槽轮廓并且在沟槽轮廓中包括栅极氧化物层，并且在栅极氧化物层上包括多晶硅层。 沟槽式端接结构具有沟槽轮廓并且在沟槽轮廓中包括氧化物层。 具有离散特征的端接多晶硅层分离端接多晶硅层。 隔离层覆盖终端多晶硅层并填充离散特征。 沟槽型MOSFET和沟槽型端接结构可以形成在包括N +硅衬底，N +硅衬底上的N外延层和N外延层上的P外延层的DMOS器件上。 沟槽型MOSFET和沟槽型端接结构的沟槽轮廓可以穿透P外延层进入N外延层。

公开(公告)号：US06677223B2

公开(公告)日：2004-01-13

申请号：US10219092

申请日：2002-08-13

Applicant: Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Hsin-Huang Hsieh

Inventor： Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Hsin-Huang Hsieh

IPC: H01L2120

CPC classification number: H01L21/28167

Abstract: Embodiments of the present invention relate to processes utilized in the manufacturing of a semiconductor device having transistors to achieve high uniformity of threshold voltages. The invention does so by ensuring high uniformity of impurity concentration in the substrate. In one embodiment, a method for manufacturing a semiconductor device having transistors with high uniformity of threshold voltages comprises providing a substrate and a source of impurities, and disposing the substrate and the source of impurities in a first oxygen gas at a first initial temperature and heated to a first target temperature at a first temperature rate to drive the impurities into the substrate. The first initial temperature is sufficiently low to prevent the oxygen from diffusing into the substrate. The substrate is disposed in a second oxygen gas at a second initial temperature and heated to a second target temperature at a second rate to form an oxide layer on the substrate. The second rate is high enough for rapid formation of the oxide layer on the substrate so as to prevent the impurities driven into the substrate from diffusing out from the substrate.

Abstract translation: 本发明的实施例涉及用于制造具有晶体管以实现阈值电压的高均匀性的半导体器件的工艺。 本发明通过确保衬底中杂质浓度的高均匀性来实现。 在一个实施例中，制造具有高阈值电压均匀性的晶体管的半导体器件的方法包括提供衬底和杂质源，并将衬底和杂质源置于第一初始温度的第一氧气中并加热 以第一温度速率升至第一目标温度以驱动杂质进入基板。 第一初始温度足够低以防止氧扩散到基底中。 将衬底在第二初始温度下设置在第二氧气中，并以第二速率加热至第二目标温度，以在衬底上形成氧化物层。 第二速率足够高以快速形成衬底上的氧化物层，以防止驱动到衬底中的杂质从衬底扩散出来。

公开(公告)号：US08368140B2

公开(公告)日：2013-02-05

申请号：US12630088

申请日：2009-12-03

Applicant: Chiao-Shun Chuang

Inventor： Chiao-Shun Chuang

IPC: H01L29/66

CPC classification number: H01L29/7827 ,  H01L27/0727

Abstract: In one embodiment the present invention includes a semiconductor device. The semiconductor device comprises a first semiconductor region, a second semiconductor region and a trench region. The first semiconductor region is of a first conductivity type and a first conductivity concentration. The trench region includes a metal layer in contact with the first semiconductor region to form a metal-semiconductor junction. The second semiconductor region is adjacent to the first semiconductor region that has a second conductivity type and a second conductivity concentration. The second semiconductor region forms a PN junction with the first semiconductor region, and the trench region has a depth such that the metal-semiconductor junction is proximate to the PN junction.

Abstract translation: 在一个实施例中，本发明包括半导体器件。 半导体器件包括第一半导体区域，第二半导体区域和沟槽区域。 第一半导体区域是第一导电类型和第一电导率浓度。 沟槽区域包括与第一半导体区域接触以形成金属 - 半导体结的金属层。 第二半导体区域与具有第二导电类型和第二电导率浓度的第一半导体区域相邻。 第二半导体区域与第一半导体区域形成PN结，并且沟槽区域具有使得金属 - 半导体结接近PN结的深度。

公开(公告)号：US06989306B2

公开(公告)日：2006-01-24

申请号：US10771808

申请日：2004-02-03

Applicant: Chiao-Shun Chuang ,  Hsin-Huang Hsieh ,  Mao-Song Tseng ,  Chien-Ping Chang

Inventor： Chiao-Shun Chuang ,  Hsin-Huang Hsieh ,  Mao-Song Tseng ,  Chien-Ping Chang

IPC: H01L21/336

CPC classification number: H01L29/7811 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7813

Abstract: Embodiments of the invention provide a termination structure of DMOS device and a method of forming the same. In forming the termination structure, a silicon substrate with an epitaxial layer formed thereon is provided. A body region defined by doping the epitaxial layer is then selectively etched to form a plurality of DMOS trenches therein. Thereafter, a gate oxide layer is formed over exposed surfaces in the body region and a termination oxide layer is formed to encircle the body region. Afterward, a polysilicon layer is deposited over all the exposed surfaces, and then selectively etched to form a plurality of poly gates in the DMOS trenches and a polysilicon plate having an extending portion toward the body region over the termination oxide layer. By using the termination polysilicon layer as an implantation mask, sources are formed in the body region. Afterward, an isolation layer and a source metal contact layer are deposited over the structure, in which the isolation layer is utilized to protect the polysilicon gates, and also the source metal contact layer is utilized to ground both the body region and the polysilicon plate.

Abstract translation: 本发明的实施例提供了一种DMOS器件的端接结构及其形成方法。 在形成端接结构时，提供其上形成有外延层的硅衬底。 然后选择性地蚀刻通过掺杂外延层限定的体区，以在其中形成多个DMOS沟槽。 此后，在体区域中的暴露表面上形成栅极氧化物层，并且形成终止氧化物层以环绕身体区域。 之后，在所有暴露的表面上沉积多晶硅层，然后选择性地蚀刻以在DMOS沟槽中形成多个多晶硅栅极，以及在端接氧化物层上具有朝向主体区域的延伸部分的多晶硅板。 通过使用终止多晶硅层作为注入掩模，在体区域中形成源。 之后，在结构上沉积隔离层和源极金属接触层，其中隔离层用于保护多晶硅栅极，并且源极金属接触层用于接地体区域和多晶硅板。

公开(公告)号：US20050199952A1

公开(公告)日：2005-09-15

申请号：US11056450

申请日：2005-02-11

Applicant: Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

Inventor： Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Su-Wen Chang ,  Mao-Song Tseng

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L31/119

CPC classification number: H01L29/7813 ,  H01L29/0661 ,  H01L29/41766 ,  H01L29/7802

Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench. A metal layer covers portions of the passivation layer on the side walls of the trench to expose a part of the passivation layer over the bottom surface of the trench.

公开(公告)号：US06821913B2

公开(公告)日：2004-11-23

申请号：US10232260

申请日：2002-08-29

Applicant: Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Cheng-Tsung Ni

Inventor： Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng ,  Cheng-Tsung Ni

IPC: H01L2131

CPC classification number: H01L29/66734 ,  H01L21/0274 ,  H01L21/76224 ,  H01L29/42368

Abstract: Embodiments of the present invention are directed to an improved method for forming dual oxide layers at the bottom of a trench of a substrate. A substrate has a trench which includes a bottom and a sidewall. The trench may be created by forming a mask oxide layer on the substrate; defining the mask oxide layer to form a patterned mask oxide layer and exposing a partial surface of the substrate to form a window; and using the patterned mask oxide layer as an etching mask to form the trench in the window. A first oxide layer is formed on the sidewall and the bottom of the trench of the substrate. A photoresist layer is formed on the substrate, filling the trench of the substrate. The method further comprises partially etching back the photoresist layer to leave a remaining photoresist layer in the trench. The height of the remaining photoresist layer is lower than the depth of the trench. A curing treatment of the remaining photoresist layer is performed after the partial etching. The patterned mask oxide layer and a portion of the first oxide layer are removed to leave a remaining first oxide layer at the bottom of the trench. The remaining photoresist layer is removed. A second oxide layer is formed on the substrate covering at least the remaining first oxide layer to form the dual oxide layers at the bottom of the trench.

Abstract translation: 本发明的实施例涉及一种用于在衬底的沟槽的底部形成双重氧化物层的改进方法。 衬底具有包括底部和侧壁的沟槽。 可以通过在衬底上形成掩模氧化物层来形成沟槽; 限定所述掩模氧化物层以形成图案化掩模氧化物层并暴露所述衬底的部分表面以形成窗口; 并且使用图案化的掩模氧化物层作为蚀刻掩模以在窗口中形成沟槽。 第一氧化物层形成在衬底的沟槽的侧壁和底部上。 在衬底上形成光刻胶层，填充衬底的沟槽。 该方法还包括部分地蚀刻光致抗蚀剂层以在沟槽中留下残留的光致抗蚀剂层。 剩余的光致抗蚀剂层的高度低于沟槽的深度。 在部分蚀刻之后进行剩余光致抗蚀剂层的固化处理。 图案化的掩模氧化物层和第一氧化物层的一部分被去除以在沟槽的底部留下剩余的第一氧化物层。 去除剩余的光致抗蚀剂层。 在衬底上形成第二氧化物层，至少覆盖剩余的第一氧化物层，以在沟槽的底部形成双氧化层。

公开(公告)号：US08314471B2

公开(公告)日：2012-11-20

申请号：US12620473

申请日：2009-11-17

Applicant: Chiao-Shun Chuang ,  Tony Huang

Inventor： Chiao-Shun Chuang ,  Tony Huang

IPC: H01L29/02

CPC classification number: H01L29/7813 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, the present invention includes a semiconductor power device. The semiconductor power device comprises a trenched gate and a trenched field region. The trenched gate is disposed vertically within a trench in a semiconductor substrate. The trenched field region is disposed vertically within the trench and below the trenched gate. A lower portion of the trenched field region tapers to disperse an electric field.

Abstract translation: 在一个实施例中，本发明包括半导体功率器件。 半导体功率器件包括沟槽栅极和沟槽场区域。 沟槽栅极垂直设置在半导体衬底的沟槽内。 沟槽场区域垂直设置在沟槽内并且在沟槽栅极下方。 沟槽场区域的下部逐渐变细以分散电场。

公开(公告)号：US07084457B2

公开(公告)日：2006-08-01

申请号：US10774212

申请日：2004-02-05

Applicant: Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng

Inventor： Hsin-Huang Hsieh ,  Chiao-Shun Chuang ,  Chien-Ping Chang ,  Mao-Song Tseng

IPC: H01L29/76 ,  H01L31/062

CPC classification number: H01L29/7811 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7813

Abstract: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.

Abstract translation: 引入了具有沟槽总线结构的DMOS器件。 沟槽总线结构包括形成在P基板上的场氧化物层和从场氧化物层的顶表面向下延伸到P衬底的下部的沟槽。 形成栅极氧化层和多晶硅母线，以填充沟槽作为总线结构的主要部分。 此外，在多晶硅总线和场氧化物层的顶部形成隔离层和金属线。 在隔离层中形成开口以形成多晶硅母线和金属线之间的连接。 在具体实施例中，同时形成DMOS器件的总线沟槽和栅极沟槽，同时形成多晶硅母线和栅电极。 因此，总线结构能够形成DMOS晶体管，而不需要用于定义多晶硅总线位置的任何光刻步骤。