利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

65 条记录 (耗时 0.049 秒)

    Method and system for scrubbing an isolated area of memory after reset of a processor operating in isolated execution mode if a cleanup flag is set
    14.
    发明授权
    Method and system for scrubbing an isolated area of memory after reset of a processor operating in isolated execution mode if a cleanup flag is set 有权
    如果设置了清除标志，则在分离执行模式下操作的处理器复位后，擦除存储器隔离区域的方法和系统

    公开(公告)号：US06754815B1

    公开(公告)日：2004-06-22

    申请号：US09618659

    申请日：2000-07-18

    申请人： Carl M. Ellison ,  Roger A. Golliver ,  Howard C. Herbert ,  Derrick C. Lin ,  Francis X. McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James A. Sutton ,  Shreekant S. Thakkar ,  Millind Mittal

    发明人： Carl M. Ellison ,  Roger A. Golliver ,  Howard C. Herbert ,  Derrick C. Lin ,  Francis X. McKeen ,  Gilbert Neiger ,  Ken Reneris ,  James A. Sutton ,  Shreekant S. Thakkar ,  Millind Mittal

    IPC分类号： G06F15177

    CPC分类号： G06F21/74 ,  G06F9/4401 ,  G06F21/62 ,  G06F2221/2143

    摘要： The present invention provides a method, apparatus, and system for invoking a reset process in response to a processor being individually reset. The reset processor operates within a platform in an isolated execution mode and is associated with an isolated area of memory. An initialization process is invoked for an initializing processor. The initialization process determines whether or not a cleanup flag is set. If the cleanup flag is set, the isolated area of memory is scrubbed. In one embodiment, when a last processor operating in the platform is reset, it is reset without clearing the cleanup flag. Subsequently, an initializing processor invokes the initialization process. The initialization process determines that the cleanup flag is set. The initialization process invokes the execution of a processor nub loader. If the cleanup flag is set, the processor nub loader scrubs the isolated area of memory and invokes a controlled close for the initializing processor. The controlled close clears the cleanup flag. The initializing processor then re-performs the initialization process. Upon the second iteration of the initialization process, with the cleanup flag not set, a new isolated area of memory is created for the initializing processor.

    摘要翻译： 本发明提供了一种响应于处理器被单独复位来调用复位过程的方法，装置和系统。 复位处理器在孤立执行模式的平台内运行，并与存储器的隔离区域相关联。 初始化处理器调用初始化过程。 初始化过程确定是否设置清除标志。 如果清除标志置位，则清除隔离区的内存。 在一个实施例中，当在平台中操作的最后一个处理器被重置时，它被重置而不清除清除标志。 随后，初始化处理器调用初始化过程。 初始化过程确定清除标志被设置。 初始化过程调用处理器nub加载器的执行。 如果清除标志置位，则处理器nub加载器将擦除存储器的隔离区域，并为初始化处理器调用受控关闭。 受控关闭清除清除标志。 初始化处理器然后重新执行初始化过程。 在初始化过程的第二次迭代时，在清除标志未设置的情况下，为初始化处理器创建一个新的隔离区域。

    Integrated circuit chip having primary and secondary random access memories for a hierarchical cache
    15.
    发明授权
    Integrated circuit chip having primary and secondary random access memories for a hierarchical cache 失效
    集成电路芯片，具有用于分级高速缓存的主和次级随机存取存储器

    公开(公告)号：US5285323A

    公开(公告)日：1994-02-08

    申请号：US61273

    申请日：1993-05-13

    申请人： Ricky C. Hetherington ,  Francis X. McKeen ,  Joseph D. Marci ,  Tryggve Fossum ,  Joel S. Emer

    发明人： Ricky C. Hetherington ,  Francis X. McKeen ,  Joseph D. Marci ,  Tryggve Fossum ,  Joel S. Emer

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0897 ,  Y02B60/1225

    摘要： A hierarchical cache memory includes a high-speed primary cache memory and a lower speed secondary cache memory of greater storage capacity than the primary cache memory. To manage a huge number of data lines interconnecting the primary and secondary cache memories, the hierarchical cache memory is integrated on a plurality of integrated circuits which include all of the interconnecting data lines. Each integrated circuit includes a primary memory and a secondary memory for storing and retrieving data transferred over a first data input line and a first data output line that link the primary memory to a central processing unit. At any given time, a multi-bit word is addressed in the secondary memory, and a corresponding multi-bit word is addressed in the primary memory. The primary and secondary memories are interconnected by a first multi-line bus for transferring a multi-bit word read from the secondary memory to the primary memory, and by a second multi-line bus for transferring a multi-bit word read from the primary memory to the secondary memory. The secondary memory is linked to a main memory by a second data output line and a second data input line for sequential transmission of bits to exchange multi-bit words during a writeback and refill operation. In a preferred embodiment, data inputs of the primary memory and the secondary memory are wired in parallel to a serial-parallel shift register that is used as a common write buffer.

    摘要翻译： 分级缓存存储器包括高于主高速缓冲存储器的高速主缓存存储器和比主高速缓存存储器更大存储容量的较低速次级高速缓冲存储器。 为了管理互连主要和次要高速缓冲存储器的大量数据线，分层高速缓冲存储器集成在包括所有互连数据线的多个集成电路上。 每个集成电路包括主存储器和辅助存储器，用于存储和检索通过第一数据输入线传送的数据和将主存储器链接到中央处理单元的第一数据输出线。 在任何给定的时间，多位字在二级存储器中寻址，并且在主存储器中寻址相应的多位字。 主存储器和次存储器通过第一多行总线互连，用于将从副存储器读取的多位字传送到主存储器，以及用于传送从主存储器读取的多位字的第二多行总线 内存到二级内存。 次存储器通过第二数据输出线和第二数据输入线链接到主存储器，用于在写回和再填充操作期间顺序传输位以交换多位字。 在优选实施例中，主存储器和次存储器的数据输入与用作公共写入缓冲器的串行 - 并行移位寄存器并联布线。

    SUPPORTING CONFIGURABLE SECURITY LEVELS FOR MEMORY ADDRESS RANGES
    17.
    发明申请
    SUPPORTING CONFIGURABLE SECURITY LEVELS FOR MEMORY ADDRESS RANGES 有权
    支持存储地址范围的可配置安全级别

    公开(公告)号：US20170024573A1

    公开(公告)日：2017-01-26

    申请号：US14803956

    申请日：2015-07-20

    申请人： Binata Bhattacharyya ,  Raghunandan Makaram ,  Amy L. Santoni ,  George Z. Chrysos ,  Simon P. Johnson ,  Brian S. Morris ,  Francis X. McKeen

    发明人： Binata Bhattacharyya ,  Raghunandan Makaram ,  Amy L. Santoni ,  George Z. Chrysos ,  Simon P. Johnson ,  Brian S. Morris ,  Francis X. McKeen

    IPC分类号： G06F21/62 ,  G06F21/60

    CPC分类号： G06F21/62 ,  G06F21/602 ,  G06F21/64 ,  G06F21/78 ,  G06F2221/2113

    摘要： A processor implementing techniques for supporting configurable security levels for memory address ranges is disclosed. In one embodiment, the processor includes a processing core a memory controller, operatively coupled to the processing core, to access data in an off-chip memory and a memory encryption engine (MEE) operatively coupled to the memory controller. The MEE is to responsive to detecting a memory access operation with respect to a memory location identified by a memory address within a memory address range associated with the off-chip memory, identify a security level indicator associated with the memory location based on a value stored on a security range register. The MEE is further to access at least a portion of a data item associated with the memory address range of the off-chip memory in view of the security level indicator.

    摘要翻译： 公开了一种实现用于支持存储器地址范围的可配置安全级别的技术的处理器。 在一个实施例中，处理器包括处理核心，存储器控制器，可操作地耦合到处理核心，以访问片外存储器中的数据和可操作地耦合到存储器控制器的存储器加密引擎（MEE）。 所述MEE响应于检测相对于与所述片外存储器相关联的存储器地址范围内的存储器地址识别的存储器位置的存储器访问操作，基于存储的值来识别与所述存储器位置相关联的安全级别指示符 在安全范围寄存器上。 鉴于安全级别指示符，MEE进一步访问与片外存储器的存储器地址范围相关联的数据项的至少一部分。