公开(公告)号：US09430384B2

公开(公告)日：2016-08-30

申请号：US13854107

申请日：2013-03-31

申请人： Carlos V Rozas ,  Ilya Alexandrovich ,  Ittai Anati ,  Alex Berenzon ,  Michael A Goldsmith ,  Barry E Huntley ,  Anton Ivanov ,  Simon P Johnson ,  Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Gilbert Neiger ,  Rinat Rappoport ,  Scott Dion Rodgers ,  Uday R. Savagaonkar ,  Vincent R. Scarlata ,  Vedvyas Shanbhogue ,  Wesley H Smith ,  William Colin Wood

发明人： Carlos V Rozas ,  Ilya Alexandrovich ,  Ittai Anati ,  Alex Berenzon ,  Michael A Goldsmith ,  Barry E Huntley ,  Anton Ivanov ,  Simon P Johnson ,  Rebekah M. Leslie-Hurd ,  Francis X. McKeen ,  Gilbert Neiger ,  Rinat Rappoport ,  Scott Dion Rodgers ,  Uday R. Savagaonkar ,  Vincent R. Scarlata ,  Vedvyas Shanbhogue ,  Wesley H Smith ,  William Colin Wood

IPC分类号： G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0875 ,  G06F12/0808 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/402

摘要： Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.

摘要翻译： 说明和逻辑为安全的飞地页面缓存提供了高级分页功能。 实施例包括多个硬件线程或处理核心，用于存储分配给由硬件线程可访问的安全空间的共享页面地址的安全数据的高速缓存。 解码级将指定所述共享页地址的第一指令解码为操作数，并且执行单元标记对应于共享页地址的飞地页高速缓存映射的条目，以阻止所述第一或第二硬件线程中的任一个的新转换的创建 访问共享页面。 第二指令被解码以执行，第二指令指定所述安全飞地作为操作数，并且执行单元记录当前访问与安全飞地相对应的飞地页面缓存中的安全数据的硬件线程，并且当任何 的硬件线程退出安全飞地。

公开(公告)号：US07849465B2

公开(公告)日：2010-12-07

申请号：US11134687

申请日：2005-05-19

申请人： Xiang Zou ,  Hong Wang ,  Scott Dion Rodgers ,  Darrell D. Boggs ,  Bryant Bigbee ,  Shivanandan Kaushik ,  Anil Aggarwal ,  Ittai Anati ,  Doron Orenstein ,  Per Hammarlund ,  John Shen ,  Larry O. Smith ,  James B. Crossland ,  Chris J. Newburn

发明人： Xiang Zou ,  Hong Wang ,  Scott Dion Rodgers ,  Darrell D. Boggs ,  Bryant Bigbee ,  Shivanandan Kaushik ,  Anil Aggarwal ,  Ittai Anati ,  Doron Orenstein ,  Per Hammarlund ,  John Shen ,  Larry O. Smith ,  James B. Crossland ,  Chris J. Newburn

IPC分类号： G06F9/46 ,  G06F13/24 ,  G06F7/38

CPC分类号： G06F9/3851 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/4843 ,  G06F11/3409 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

摘要： Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.

摘要翻译： 用于可激活其他线程的可编程事件驱动产量机制的方法，装置和系统。 收益机制可以允许在出现体系结构定义的条件时触发可以执行当前与主线程的服务线程。 响应于条件，可以在操作系统的有限干预下激活服务线程。 在一个实施例中，装置包括执行多个指令的执行资源和监视器以检测体系结构定义的条件。 该装置可以包括事件处理程序，用于处理当检测到体系结构定义的条件时产生的产出事件。 可以使用包括处理器指令和通道寄存器在内的架构机制来允许用户级代码来实现产出事件机制。 还描述和要求保护其他实施例。

公开(公告)号：US08762694B1

公开(公告)日：2014-06-24

申请号：US11395884

申请日：2006-03-31

申请人： Xiang Zou ,  Hong Wang ,  Robert Knight ,  Robert Geva ,  Gautham Chinya ,  Scott Dion Rodgers ,  Chris Newburn ,  Bryant E. Bigbee ,  Per Hammarlund ,  Ittai Anati ,  Jim B. Crossland ,  John P. Shen

发明人： Xiang Zou ,  Hong Wang ,  Robert Knight ,  Robert Geva ,  Gautham Chinya ,  Scott Dion Rodgers ,  Chris Newburn ,  Bryant E. Bigbee ,  Per Hammarlund ,  Ittai Anati ,  Jim B. Crossland ,  John P. Shen

IPC分类号： G06F9/48

CPC分类号： G06F9/3851 ,  G06F9/3009 ,  G06F9/4843 ,  G06F11/3409 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

摘要： Method, apparatus, and system for a programmable event-driven yield mechanism. The mechanism may disrupt processing of a program to deliver a yield event. The event may be treated as a fault-like yield event or a trap-like event. For a fault-like yield event, the faulting instruction is canceled before retirement and processor state is not updated before the yield event is delivered. For a trap-like yield event the instruction causing the trap is retired and the yield event is delivered on an interrupt boundary. Multiple pending yield events may be handled according to priority. Other embodiments are also described and claimed.

摘要翻译： 用于可编程事件驱动产出机制的方法，装置和系统。 该机制可能会中断处理程序以传递yield事件。 事件可能被视为类似故障的收益事件或类似陷阱的事件。 对于类似故障的产出事件，在退出之前取消故障指令，并且在发送收益事件之前未更新处理器状态。 对于类似陷阱的收益事件，导致陷阱的指令将被退出，并且收益事件在中断边界上传递。 可以根据优先级处理多个待处理的收益事件。 还描述和要求保护其他实施例。

公开(公告)号：US20180196759A1

公开(公告)日：2018-07-12

申请号：US15912405

申请日：2018-03-05

申请人： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

发明人： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC分类号： G06F12/1027 ,  G06F12/02 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1045 ,  G06F9/455

CPC分类号： G06F12/1027 ,  G06F9/30047 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US20180196758A1

公开(公告)日：2018-07-12

申请号：US15912363

申请日：2018-03-05

申请人： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

发明人： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron Rust ,  Sebastian Schoenberg

IPC分类号： G06F12/1027 ,  G06F12/02 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1045 ,  G06F9/455

摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US08635415B2

公开(公告)日：2014-01-21

申请号：US12571269

申请日：2009-09-30

申请人： Baiju V. Patel ,  Rajeev Gopalakrishna ,  Andrew F. Glew ,  Robert J. Kushlis ,  Don Alan Van Dyke ,  Joseph Frank Cihula ,  Asit K. Mallick ,  James B. Crossland ,  Gilbert Neiger ,  Scott Dion Rodgers ,  Martin Guy Dixon ,  Mark Jay Charney ,  Jacob (Koby) Gottlieb

发明人： Baiju V. Patel ,  Rajeev Gopalakrishna ,  Andrew F. Glew ,  Robert J. Kushlis ,  Don Alan Van Dyke ,  Joseph Frank Cihula ,  Asit K. Mallick ,  James B. Crossland ,  Gilbert Neiger ,  Scott Dion Rodgers ,  Martin Guy Dixon ,  Mark Jay Charney ,  Jacob (Koby) Gottlieb

IPC分类号： G06F12/02 ,  G06F9/302

CPC分类号： G06F9/3013 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/32 ,  G06F9/342 ,  G06F9/35 ,  G06F12/1441

摘要： A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.

摘要翻译： 一组处理器的默认寄存器被扩展到计算机系统的处理器上的元数据寄存器。 存储有数据的默认寄存器，而与数据相关的元数据分别存储在元数据寄存器上。

公开(公告)号：US08601233B2

公开(公告)日：2013-12-03

申请号：US13658752

申请日：2012-10-23

申请人： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A. Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron B. Rust ,  Sebastian Schoenberg

发明人： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Richard A. Uhlig ,  Scott Dion Rodgers ,  Rajesh M. Sankaran ,  Camron B. Rust ,  Sebastian Schoenberg

IPC分类号： G11C15/00

CPC分类号： G06F12/1027 ,  G06F9/3004 ,  G06F9/30076 ,  G06F9/45558 ,  G06F12/0246 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1036 ,  G06F12/1054 ,  G06F2009/45583 ,  G06F2212/152 ,  G06F2212/2022 ,  G06F2212/452 ,  G06F2212/50 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/7201

摘要： A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

公开(公告)号：US20110078389A1

公开(公告)日：2011-03-31

申请号：US12571269

申请日：2009-09-30

申请人： Baiju V. Patel ,  Rajeev Gopalakrishna ,  Andrew F. Glew ,  Robert J. Kushlis ,  Don Alan Van Dyke ,  Joseph Frank Cihula ,  Asit K. Mallick ,  James B. Crossland ,  Gilbert Neiger ,  Scott Dion Rodgers ,  Martin Guy Dixon ,  Mark Jay Charney ,  Jocob Gottlieb

发明人： Baiju V. Patel ,  Rajeev Gopalakrishna ,  Andrew F. Glew ,  Robert J. Kushlis ,  Don Alan Van Dyke ,  Joseph Frank Cihula ,  Asit K. Mallick ,  James B. Crossland ,  Gilbert Neiger ,  Scott Dion Rodgers ,  Martin Guy Dixon ,  Mark Jay Charney ,  Jocob Gottlieb

IPC分类号： G06F9/30 ,  G06F12/02 ,  G06F9/302

CPC分类号： G06F9/3013 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/32 ,  G06F9/342 ,  G06F9/35 ,  G06F12/1441

摘要： A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.

摘要翻译： 一组处理器的默认寄存器被扩展到计算机系统的处理器上的元数据寄存器。 存储有数据的默认寄存器，而与数据相关的元数据分别存储在元数据寄存器上。

公开(公告)号：US20160019067A1

公开(公告)日：2016-01-21

申请号：US14866875

申请日：2015-09-26

申请人： Hong Wang ,  John P. Shen ,  Edward T. Grochowski ,  Richard A. Hankins ,  Gautham N. Chinya ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju V. Patel ,  James P Held

发明人： Hong Wang ,  John P. Shen ,  Edward T. Grochowski ,  Richard A. Hankins ,  Gautham N. Chinya ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju V. Patel ,  James P Held

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3867 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/4843 ,  G06F9/4881

摘要： In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

公开(公告)号：US20130132636A1

公开(公告)日：2013-05-23

申请号：US13690931

申请日：2012-11-30

申请人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

发明人： Jasmin Ajanovic ,  Mahesh Wagh ,  Prashant Sethi ,  Debendra Das Sharma ,  David J. Harriman ,  Mark B. Rosenbluth ,  Ajay V. Bhatt ,  Peter Barry ,  Scott Dion Rodgers ,  Anil Vasudevan ,  Sridhar Muthrasanallur ,  James Akiyama ,  Robert G. Blankenship ,  Ohad Falik ,  Avi Mendelson ,  Ilan Pardo ,  Eran Tamari ,  Eliezer Weissmann ,  Doron Shamia

IPC分类号： G06F13/42

CPC分类号： G06F12/0831 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F12/0815 ,  G06F13/385 ,  G06F13/4045 ,  G06F13/4068 ,  G06F13/4265 ,  G06F2212/621 ,  H04L12/66 ,  Y02D10/126 ,  Y02D10/151

摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.