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    Integrated circuit chip having primary and secondary random access memories for a hierarchical cache
    1.
    发明授权
    Integrated circuit chip having primary and secondary random access memories for a hierarchical cache 失效
    集成电路芯片，具有用于分级高速缓存的主和次级随机存取存储器

    公开(公告)号：US5285323A

    公开(公告)日：1994-02-08

    申请号：US61273

    申请日：1993-05-13

    申请人： Ricky C. Hetherington ,  Francis X. McKeen ,  Joseph D. Marci ,  Tryggve Fossum ,  Joel S. Emer

    发明人： Ricky C. Hetherington ,  Francis X. McKeen ,  Joseph D. Marci ,  Tryggve Fossum ,  Joel S. Emer

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0897 ,  Y02B60/1225

    摘要： A hierarchical cache memory includes a high-speed primary cache memory and a lower speed secondary cache memory of greater storage capacity than the primary cache memory. To manage a huge number of data lines interconnecting the primary and secondary cache memories, the hierarchical cache memory is integrated on a plurality of integrated circuits which include all of the interconnecting data lines. Each integrated circuit includes a primary memory and a secondary memory for storing and retrieving data transferred over a first data input line and a first data output line that link the primary memory to a central processing unit. At any given time, a multi-bit word is addressed in the secondary memory, and a corresponding multi-bit word is addressed in the primary memory. The primary and secondary memories are interconnected by a first multi-line bus for transferring a multi-bit word read from the secondary memory to the primary memory, and by a second multi-line bus for transferring a multi-bit word read from the primary memory to the secondary memory. The secondary memory is linked to a main memory by a second data output line and a second data input line for sequential transmission of bits to exchange multi-bit words during a writeback and refill operation. In a preferred embodiment, data inputs of the primary memory and the secondary memory are wired in parallel to a serial-parallel shift register that is used as a common write buffer.

    摘要翻译： 分级缓存存储器包括高于主高速缓冲存储器的高速主缓存存储器和比主高速缓存存储器更大存储容量的较低速次级高速缓冲存储器。 为了管理互连主要和次要高速缓冲存储器的大量数据线，分层高速缓冲存储器集成在包括所有互连数据线的多个集成电路上。 每个集成电路包括主存储器和辅助存储器，用于存储和检索通过第一数据输入线传送的数据和将主存储器链接到中央处理单元的第一数据输出线。 在任何给定的时间，多位字在二级存储器中寻址，并且在主存储器中寻址相应的多位字。 主存储器和次存储器通过第一多行总线互连，用于将从副存储器读取的多位字传送到主存储器，以及用于传送从主存储器读取的多位字的第二多行总线 内存到二级内存。 次存储器通过第二数据输出线和第二数据输入线链接到主存储器，用于在写回和再填充操作期间顺序传输位以交换多位字。 在优选实施例中，主存储器和次存储器的数据输入与用作公共写入缓冲器的串行 - 并行移位寄存器并联布线。

    Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements
    2.
    发明授权
    Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements 失效
    使用高速缓存和主存储器的方法和装置，用于通过预取包括向量数据元素的高速缓存块来进行矢量处理和标量处理

    公开(公告)号：US4888679A

    公开(公告)日：1989-12-19

    申请号：US142794

    申请日：1988-01-11

    申请人： Tryggve Fossum ,  Ricky C. Hetherington ,  David B. Fite, Jr. ,  Dwight P. Manley ,  Francis X. McKeen ,  John E. Murray

    发明人： Tryggve Fossum ,  Ricky C. Hetherington ,  David B. Fite, Jr. ,  Dwight P. Manley ,  Francis X. McKeen ,  John E. Murray

    IPC分类号： G06F12/06 ,  G06F9/38 ,  G06F12/02 ,  G06F12/08 ,  G06F15/78 ,  G06F17/16

    CPC分类号： G06F15/8069 ,  G06F12/0207 ,  G06F12/0855 ,  G06F9/3455 ,  G06F9/383

    摘要： A main memory and cache suitable for scalar processing are used in connection with a vector processor by issuing prefetch requests in response to the recognition of a vector load instruction. A respective prefetch request is issued for each block containing an element of the vector to be loaded from memory. In response to a prefetch request, the cache is checked for a "miss" and if the cache does not include the required block, a refill request is sent to the main memory. The main memory is configured into a plurality of banks and has a capability of processing multiple references. Therefore the different banks can be referenced simultaneously to prefetch multiple blocks of vector data. Preferably a cache bypass is provided to transmit data directly to the vector processor as the data from the main memory are being stored in the cache. In a preferred embodiment, a vector processor is added to a digital computing system including a scalar processor, a virtual address translation buffer, a main memory and a cache. The scalar processor includes a microcode interpreter which sends a vector load command to the vector processing unit and which also generates vector prefetch requests. The addresses for the data blocks to be prefetched are computed based upon the vector address, the length of the vector and the "stride" or spacing between the addresses of the elements of the vector.

    摘要翻译： 适用于标量处理的主存储器和缓存器与矢量处理器结合使用以响应于矢量加载指令的识别发出预取请求。 为包含要从存储器加载的向量的元素的每个块发出相应的预取请求。 响应于预取请求，检查缓存是否存在“未命中”，并且如果高速缓存不包括所需的块，则向主存储器发送补充请求。 主存储器被配置成多个存储体并且具有处理多个引用的能力。 因此，可以同时引用不同的库来预取多个向量数据块。 优选地，提供高速缓存旁路以将数据直接发送到向量处理器，因为来自主存储器的数据正被存储在高速缓存中。 在优选实施例中，将向量处理器添加到包括标量处理器，虚拟地址转换缓冲器，主存储器和高速缓存的数字计算系统。 标量处理器包括微代码解释器，其向向量处理单元发送向量加载命令，并且还生成向量预取请求。 要预取的数据块的地址是基于向量地址，向量的长度和向量元素的地址之间的“stride”或间距来计算的。

    Write back buffer with error correcting capabilities
    7.
    发明授权
    Write back buffer with error correcting capabilities 失效
    回写具有纠错功能的缓冲区

    公开(公告)号：US4995041A

    公开(公告)日：1991-02-19

    申请号：US306703

    申请日：1989-02-03

    申请人： Ricky C. Hetherington ,  Tryggve Fossum ,  Maurice B. Steinman ,  David A. Webb, Jr.

    发明人： Ricky C. Hetherington ,  Tryggve Fossum ,  Maurice B. Steinman ,  David A. Webb, Jr.

    IPC分类号： G06F11/10 ,  G06F12/08 ,  G06F12/16

    CPC分类号： G06F11/1048 ,  G06F11/1064 ,  G06F12/0804

    摘要： In the operation of high-speed computers, it is frequently advantageous to employ a high speed cache memory within each CPU of a multiple CPU computer system. A standard, slower memory configuration remains in use for the large, common main memory, but those portions of main memory which are expected to be used heavily are copied into the cache memory. Thus, on many memory references, the faster cache memory is exploited, while only infrequent references to the slower main memory are necessary. This configuration generally speeds the overall operation of the computer system; however, memory integrity problems arise by maintaining two separate copies of selected portions of main memory. Accordingly, the memory access unit of the CPU uses error correction code (ECC) hardware to ensure the integrity of the data delivered between the cache and main memory. The prevent the ECC hardware from slowing the overall operation of the CPU, the error correction is performed underneath a write back operation. Data contained in the cache, which will be displaced by data received from main memory 10, is transferred to a write back buffer (WBB) during that period of time between the request for data from the main memory and actual delivery of the requested data. Further, the ECC hardware also operates on the cache data being written to the WBB. Accordingly, a performance penalty is avoided by performing error correction and preremoving the cache data during that idle period of time.

    System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation
    8.
    发明授权
    System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation 失效
    用于通过操作存储器管理处理器来计算虚拟地址到物理地址的系统，用于计算存储器中的物理地址的位置并与高速缓存比较虚拟地址进行翻译

    公开(公告)号：US5349651A

    公开(公告)日：1994-09-20

    申请号：US746007

    申请日：1991-08-09

    申请人： Ricky C. Hetherington ,  David A. Webb, Jr. ,  David B. Fite ,  John E. Murray ,  Tryggve Fossum ,  Dwight P. Manley

    发明人： Ricky C. Hetherington ,  David A. Webb, Jr. ,  David B. Fite ,  John E. Murray ,  Tryggve Fossum ,  Dwight P. Manley

    IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/00

    CPC分类号： G06F12/0855 ,  G06F12/1045

    摘要： In the field of high speed computers it is common for a central processing unit to reference memory locations via a virtual addressing scheme, rather than by the actual physical memory addresses. In a multi-tasking environment, this virtual addressing scheme reduces the possibility of different programs accessing the same physical memory location. Thus, to maintain computer processing speed, a high speed translation buffer cache is employed to perform the necessary virtual-to-physical conversions for memory reference instructions. The translation buffer cache stores a number of previously translated virtual addresses and their corresponding physical addresses. A memory management processor is employed to update the translation buffer cache with the most recently accessed physical memory locations. The memory management processor consists of a state machine controlling hardware specifically designed for the purpose of updating the translation buffer cache. The memory management processor calculates an address of a location in the memory where the physical address is stored concurrently with the translation buffer cache comparing the virtual address with already stored virtual addresses. With this arrangement the memory management unit can immediately access memory to retrieve the physical address upon a "miss" by the translation buffer cache.

    摘要翻译： 在高速计算机领域，中央处理单元通常通过虚拟寻址方案而不是实际物理存储器地址来引用存储器位置。 在多任务环境中，这种虚拟寻址方案减少了访问相同物理内存位置的不同程序的可能性。 因此，为了维持计算机处理速度，使用高速转换缓冲器缓存来对存储器参考指令执行必要的虚拟到物理转换。 翻译缓冲区高速缓存存储多个先前转换的虚拟地址及其对应的物理地址。 使用存储器管理处理器来更新具有最近访问的物理存储器位置的翻译缓冲器高速缓存。 存储器管理处理器由控制硬件的状态机组成，其特别设计用于更新翻译缓冲器高速缓存。 存储器管理处理器计算存储器中与物理地址同时存储的位置的地址，该地址与翻译缓冲器高速缓存将虚拟地址与已存储的虚拟地址进行比较。 利用这种安排，存储器管理单元可以立即访问存储器，以在翻译缓冲器高速缓存器“遗漏”时检索物理地址。

    Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system
    9.
    发明授权
    Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system 失效
    用于确保多处理器系统中的多个高速缓冲存储器与主存储器之间的数据一致性的方案

    公开(公告)号：US5222224A

    公开(公告)日：1993-06-22

    申请号：US727296

    申请日：1991-07-09

    申请人： Michael E. Flynn ,  Scott Arnold ,  Stephen J. DeLaHunt ,  Tryggve Fossum ,  Ricky C. Hetherington ,  David J. Webb

    发明人： Michael E. Flynn ,  Scott Arnold ,  Stephen J. DeLaHunt ,  Tryggve Fossum ,  Ricky C. Hetherington ,  David J. Webb

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0822

    摘要： A method for insuring data consistency between a plurality of individual processor cache memories and the main memory in a multi-processor computer system is provided which is capable of (1) detecting when one of a set of predefined data inconsistency states occurs as a data transaction request is being processed, and (2) correcting the data inconsistency states so that the operation may be executed in a correct and consistent manner. In particular, the method is adapted to address two kinds of data inconsistency states: (1) A request for a operation from a system unit to main memory when the location to be written to is present in the cache of some processor unit-in such a case, data in the cache is "stale" and the data inconsistency is avoided by preventing the associated processor from using the "stale" data; and (2) when a read operation is requested of main memory by a system unit and the location to be read may be written or has already been written in the cache of some processor--in this case, the data in main memory is "stale" and the data inconsistency is avoided by insuring that the data returned to the requesting unit is the updated data in the cache. The presence of one of the above-described data inconsistency states is detected in a SCU-based multi-processing system by providing the SCU with means for maintaining a copy of the cache directories for each of the processor caches. The SCU continually compares address data accompanying memory access requests with what is stored in the SCU cache directories in order to determine the presence of predefined conditions indicative of data inconsistencies, and subsequently executes corresponding predefined fix-up sequences.

    摘要翻译： 提供了一种用于在多处理器计算机系统中确保多个单独处理器高速缓冲存储器与主存储器之间的数据一致性的方法，其能够（1）检测何时发生一组预定义数据不一致状态之一作为数据事务 正在处理请求，以及（2）校正数据不一致状态，以便以正确和一致的方式执行操作。 特别地，该方法适于解决两种数据不一致状态：（1）当要写入的位置存在于一些处理器单元的高速缓存中时，请求从系统单元到主存储器的操作 - 如此 一种情况下，缓存中的数据是“陈旧”的，并且通过防止相关联的处理器使用“过时”数据来避免数据不一致; 和（2）当通过系统单元请求主存储器的读取操作并且可以将待读取的位置写入或已经写入一些处理器的高速缓存中时 - 在这种情况下，主存储器中的数据是“过时的” “并且通过确保返回到请求单元的数据是高速缓存中的更新数据来避免数据不一致。 在基于SCU的多处理系统中检测到上述数据不一致状态之一的存在，通过为SCU提供用于维护每个处理器高速缓存的高速缓存目录的副本的装置。 SCU连续地将伴随存储器访问请求的地址数据与存储在SCU高速缓存目录中的内容进行比较，以便确定指示数据不一致性的预定义条件的存在，并且随后执行相应的预定义修补序列。

    Method and apparatus for ordering and queueing multiple memory requests
    10.
    发明授权
    Method and apparatus for ordering and queueing multiple memory requests 失效
    用于订购和排队多种内存请求的方法和装置

    公开(公告)号：US5222223A

    公开(公告)日：1993-06-22

    申请号：US306870

    申请日：1989-02-03

    申请人： David A. Webb, Jr. ,  Ricky C. Hetherington ,  John E. Murray ,  Tryggve Fossum ,  Dwight P. Manley

    发明人： David A. Webb, Jr. ,  Ricky C. Hetherington ,  John E. Murray ,  Tryggve Fossum ,  Dwight P. Manley

    IPC分类号： G06F12/08 ,  G06F9/38 ,  G06F12/00 ,  G06F12/10 ,  G06F13/18

    CPC分类号： G06F13/18 ,  G06F12/1054 ,  G06F9/3824

    摘要： In a pipelined computer system 10, memory access functions (requests) are simultaneously generated from a plurality of different locations. These multiple requests are passed through a multiplexer 50 according to a prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. In this manner, the complex task of converting virtual-to-physical addresses is accomplished for all memory access requests by a single translation buffer 30. The physical address output from the translation buffer 30 are passed to a cache 28 through a second multiplexer 40 according to a second prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. The first and second prioritization schemes differ, in that the memory is capable of handling other requests while a higher priority "miss" is pending. Thus, the prioritization scheme temporarily suspends the higher priority request while the desired data is being retrieved from main memory 14, but continues to operate on a lower priority request so that the overall operation will be enhanced if the lower priority request hits in the cache 28.