公开(公告)号：US07897513B2

公开(公告)日：2011-03-01

申请号：US11770593

申请日：2007-06-28

申请人： Haowen Bu ,  Shashank Ekbote ,  Juanita Deloach

发明人： Haowen Bu ,  Shashank Ekbote ,  Juanita Deloach

IPC分类号： H01L21/44

CPC分类号： H01L21/28518

摘要： The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing a metal layer on the substrate. The metal layer is annealed within a first temperature range and for a first dwell time of about 10 milliseconds or less to react at least a portion of the metal with the silicon to form a silicide. An unreacted portion of the metal is removed from the substrate. The silicide is annealed within a second temperature range for a second dwell time of about 10 milliseconds or less.

摘要翻译： 本申请涉及形成金属硅化物层的方法。 该方法包括提供包括硅的衬底并在衬底上沉积金属层。 金属层在第一温度范围内退火，并且在约10毫秒或更短的第一停留时间内使至少一部分金属与硅反应形成硅化物。 将金属的未反应部分从基材上除去。 硅化物在第二温度范围内退火约10毫秒或更短的第二停留时间。

公开(公告)号：US07537988B2

公开(公告)日：2009-05-26

申请号：US11870241

申请日：2007-10-10

申请人： Shashank Ekbote ,  Deborah J. Riley ,  Borna Obradovic

发明人： Shashank Ekbote ,  Deborah J. Riley ,  Borna Obradovic

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/823864 ,  H01L27/11

摘要： A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted. The fabrication of the integrated circuit is then completed.

摘要翻译： 制造CMOS集成电路的方法包括以下步骤：使用该表面在NMOS和PMOS区域中提供具有半导体表面的衬底，在其上形成栅极电介质和多个栅电极。 形成包括顶层和组成不同底层的多层偏移间隔堆叠，并且蚀刻多层间隔堆叠以在栅电极的侧壁上形成偏置间隔物。 设计成利用较薄的偏移间隔物的晶体管被​​第一掩模材料覆盖，并且被设计成利用更厚的偏移间隔物的晶体管被​​图案化并且首先被注入。 去除顶层的至少一部分以在栅电极的侧壁上留下较薄的偏移间隔物。 设计成利用较厚的偏移间隔物的晶体管被​​第二掩模材料覆盖，并且设计成利用较薄的偏移间隔物的晶体管被​​图案化并且被第二次注入。 然后完成集成电路的制造。

公开(公告)号：US20080179691A1

公开(公告)日：2008-07-31

申请号：US11668946

申请日：2007-01-30

申请人： Kamel Benaissa ,  Greg Baldwin ,  Shashank Ekbote

发明人： Kamel Benaissa ,  Greg Baldwin ,  Shashank Ekbote

IPC分类号： H01L27/088 ,  H01L21/77

CPC分类号： H01L21/823412 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/045 ,  H01L29/1083

摘要： An example of the present application is directed to an integrated circuit having a first plurality of transistors and a second plurality of transistors. Each of the first plurality of transistors comprises a first gate structure oriented in a first direction and each of the second plurality of transistors comprises a second gate structure oriented in a second direction. Each of the first plurality of transistors are formed with at least one more pocket region than each of the second plurality of transistors. Methods for forming the integrated circuit devices of the present application are also disclosed.

摘要翻译： 本申请的示例涉及具有第一多个晶体管和第二多个晶体管的集成电路。 第一多个晶体管中的每一个包括在第一方向上定向的第一栅极结构，并且第二多个晶体管中的每一个包括沿第二方向取向的第二栅极结构。 第一多个晶体管中的每一个形成有比第二多个晶体管中的每个晶体管的至少一个多个袋区域。 还公开了用于形成本申请的集成电路器件的方法。

公开(公告)号：US07812401B2

公开(公告)日：2010-10-12

申请号：US12688966

申请日：2010-01-18

申请人： Borna Obradovic ,  Shashank Ekbote ,  Mark Visokay

发明人： Borna Obradovic ,  Shashank Ekbote ,  Mark Visokay

IPC分类号： H01L27/092

CPC分类号： H01L29/7833 ,  H01L21/26513 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm−3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.

摘要翻译： 集成电路（IC）包括半导体衬底，形成在衬底中或衬底上的至少一个MOS晶体管，所述MOS晶体管包括掺杂有第一掺杂剂类型的源极和漏极，所述第一掺杂类型具有介于其间的第二掺杂剂类型的沟道区，以及 栅电极和沟道区上的栅极绝缘体。 形成低电阻接触的硅化物层位于源极和漏极的表面部分的界面区域。 在界面区域，第一掺杂剂的化学浓度为至少5×1020cm-3。 根据本发明的硅化物界面提供具有低硅化物界面电阻，低管密度的MOS晶体管，对短沟道行为具有可接受的小的影响。

公开(公告)号：US20090004853A1

公开(公告)日：2009-01-01

申请号：US11770593

申请日：2007-06-28

申请人： Haowen Bu ,  Shashank Ekbote ,  Juanita Deloach

发明人： Haowen Bu ,  Shashank Ekbote ,  Juanita Deloach

IPC分类号： H01L21/44

CPC分类号： H01L21/28518

摘要： The present application is directed to a method for forming a metal silicide layer. The method comprises providing a substrate comprising silicon and depositing a metal layer on the substrate. The metal layer is annealed within a first temperature range and for a first dwell time of about 10 milliseconds or less to react at least a portion of the metal with the silicon to form a silicide. An unreacted portion of the metal is removed from the substrate. The silicide is annealed within a second temperature range for a second dwell time of about 10 milliseconds or less.

摘要翻译： 本申请涉及形成金属硅化物层的方法。 该方法包括提供包括硅的衬底并在衬底上沉积金属层。 金属层在第一温度范围内退火，并且在约10毫秒或更短的第一停留时间内使至少一部分金属与硅反应形成硅化物。 将金属的未反应部分从基材上除去。 硅化物在第二温度范围内退火约10毫秒或更短的第二停留时间。

公开(公告)号：US20090263946A1

公开(公告)日：2009-10-22

申请号：US12493824

申请日：2009-06-29

申请人： Kamel Benaissa ,  Greg Baldwin ,  Shashank Ekbote

发明人： Kamel Benaissa ,  Greg Baldwin ,  Shashank Ekbote

IPC分类号： H01L21/8238

CPC分类号： H01L21/823412 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/045 ,  H01L29/1083

摘要： An example of the present application is directed to an integrated circuit having a first plurality of transistors and a second plurality of transistors. Each of the first plurality of transistors comprises a first gate structure oriented in a first direction and each of the second plurality of transistors comprises a second gate structure oriented in a second direction. Each of the first plurality of transistors are formed with at least one more pocket region than each of the second plurality of transistors. Methods for forming the integrated circuit devices of the present application are also disclosed.

摘要翻译： 本申请的示例涉及具有第一多个晶体管和第二多个晶体管的集成电路。 第一多个晶体管中的每一个包括在第一方向上定向的第一栅极结构，并且第二多个晶体管中的每一个包括沿第二方向取向的第二栅极结构。 第一多个晶体管中的每一个形成有比第二多个晶体管中的每个晶体管的至少一个多个袋区域。 还公开了用于形成本申请的集成电路器件的方法。

公开(公告)号：US20090098694A1

公开(公告)日：2009-04-16

申请号：US11928872

申请日：2007-10-30

申请人： Shashank Ekbote ,  Borna Obradovic ,  Greg C. Baldwin

发明人： Shashank Ekbote ,  Borna Obradovic ,  Greg C. Baldwin

IPC分类号： H01L21/8238 ,  H01L21/8244

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/823842 ,  H01L27/11

摘要： A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices.

摘要翻译： 一种制造CMOS集成电路的方法包括以下步骤：提供具有半导体表面的衬底，在半导体表面上形成栅极电介质层，在栅极介质层上形成多晶硅层。 图案化多晶硅层，同时未掺杂以形成包含栅极的多个多晶硅。 第一模式用于保护多个PMOS器件，并且执行第一n型注入以掺杂多个NMOS器件的栅极和源极/漏极区域。 第二模式用于保护PMOS器件以及用于多个NMOS器件的一部分的源极/漏极和栅极，并且执行第二n型注入以掺杂其它NMOS器件的栅极。

公开(公告)号：US20070218662A1

公开(公告)日：2007-09-20

申请号：US11725927

申请日：2007-03-20

申请人： Haowen Bu ,  Amitabh Jain ,  Srinivasan Chakravarthi ,  Shashank Ekbote

发明人： Haowen Bu ,  Amitabh Jain ,  Srinivasan Chakravarthi ,  Shashank Ekbote

IPC分类号： H01L21/425

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/6653 ,  H01L29/7833

摘要： A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.

摘要翻译： 公开了一种用于在半导体衬底中注入和活化锑作为掺杂剂的方法。 还公开了一种用于注入和活化锑以形成晶体管的源极/漏极延伸区域的方法，以便实现高激活并避免随后暴露于高温而失活。 该技术有助于形成非常薄的源极/漏极区域，其表现出降低的薄层电阻，同时还抑制短沟道效应。 还建议对这些技术的增强用于更精确地注入锑以产生较浅的源极/漏极延伸，并且确保形成源极/漏极延伸区域以使栅极下沉。 还公开了晶体管和其它半导体组件，其包括包含活性锑的掺杂区域，例如根据所公开的方法形成的那些。

公开(公告)号：US20060166457A1

公开(公告)日：2006-07-27

申请号：US11040749

申请日：2005-01-21

申请人： Sarah Liu ,  Greg Baldwin ,  Haowen Bu ,  Shashank Ekbote

发明人： Sarah Liu ,  Greg Baldwin ,  Haowen Bu ,  Shashank Ekbote

IPC分类号： H01L21/336

CPC分类号： H01L28/20 ,  H01L27/0629

摘要： A method for manufacturing a semiconductor wafer 10 that includes implanting source/drain regions 75 within a top surface of the semiconductor substrate 20, forming a dielectric capping layer 170 over the semiconductor wafer 20, and annealing the semiconductor wafer 10 to activate sources/drains 70. The method further includes forming a layer of photoresist 180 and then patterning the layer of photoresist 180 to protect a middle portion of the polysilicon layer 100 of the non-silicided poly resistor stacks 30, etching the exposed portions of the dielectric capping layer 170, and removing the patterned photoresist 180. A layer of silicidation metal 190 is formed over the semiconductor wafer 10, and a silicide anneal is performed to create a silicide 160 within a top surface of said sources/drains 70 and also within unprotected top portions of the polysilicon layer 100 of the non-silicided poly resistors 30. Then the remaining portions of the dielectric capping layer 170 are etched.

摘要翻译： 一种用于制造半导体晶片10的方法，其包括在半导体衬底20的顶表面内注入源极/漏极区域75，在半导体晶片20上方形成电介质覆盖层170，并且退火半导体晶片10以激活源极/漏极70 。 该方法还包括形成光致抗蚀剂层180，然后对光致抗蚀剂180的层进行图案化，以保护非硅化多电阻堆叠30的多晶硅层100的中间部分，蚀刻介电覆盖层170的暴露部分，以及 去除图案化的光致抗蚀剂180。 在半导体晶片10上形成一层硅化金属190，并且进行硅化物退火以在所述源极/漏极70的顶表面内以及非多晶硅层100的非保护顶部内形成硅化物160， 硅化聚电阻30。 然后蚀刻介电覆盖层170的剩余部分。