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公开(公告)号：US20090098695A1
公开(公告)日：2009-04-16
申请号：US11870241
申请日：2007-10-10
IPC分类号： H01L21/8238 , H01L21/8244
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/823864 , H01L27/11
摘要： A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted. The fabrication of the integrated circuit is then completed.
摘要翻译： 制造CMOS集成电路的方法包括以下步骤：使用该表面在NMOS和PMOS区域中提供具有半导体表面的衬底，在其上形成栅极电介质和多个栅电极。 形成包括顶层和组成不同底层的多层偏移间隔堆叠，并且蚀刻多层间隔堆叠以在栅电极的侧壁上形成偏置间隔物。 设计成利用较薄的偏移间隔物的晶体管被第一掩模材料覆盖，并且被设计成利用更厚的偏移间隔物的晶体管被图案化并且首先被注入。 去除顶层的至少一部分以在栅电极的侧壁上留下较薄的偏移间隔物。 设计成利用较厚的偏移间隔物的晶体管被第二掩模材料覆盖，并且设计成利用较薄的偏移间隔物的晶体管被图案化并且被第二次注入。 然后完成集成电路的制造。
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公开(公告)号：US07537988B2
公开(公告)日：2009-05-26
申请号：US11870241
申请日：2007-10-10
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/823864 , H01L27/11
摘要： A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted. The fabrication of the integrated circuit is then completed.
摘要翻译： 制造CMOS集成电路的方法包括以下步骤：使用该表面在NMOS和PMOS区域中提供具有半导体表面的衬底，在其上形成栅极电介质和多个栅电极。 形成包括顶层和组成不同底层的多层偏移间隔堆叠，并且蚀刻多层间隔堆叠以在栅电极的侧壁上形成偏置间隔物。 设计成利用较薄的偏移间隔物的晶体管被第一掩模材料覆盖，并且被设计成利用更厚的偏移间隔物的晶体管被图案化并且首先被注入。 去除顶层的至少一部分以在栅电极的侧壁上留下较薄的偏移间隔物。 设计成利用较厚的偏移间隔物的晶体管被第二掩模材料覆盖，并且设计成利用较薄的偏移间隔物的晶体管被图案化并且被第二次注入。 然后完成集成电路的制造。
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3.发明申请NITRIDE REMOVAL WHILE PROTECTING SEMICONDUCTOR SURFACES FOR FORMING SHALLOW JUNCTIONS 有权保护半导体表面的氮化物去除形成微结点公开(公告)号：US20100248440A1
公开(公告)日：2010-09-30
申请号：US12731913
申请日：2010-03-25
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , H01L29/6653 , H01L29/6656
摘要： A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sidewall spacers, LDD regions and S/D regions include an exposed silicon nitride layer. The LDD or S/D regions include a protective dielectric layer formed directly on the semiconductor surface. Ion implanting implants the LDD regions or S/D regions using the sidewall spacers as implant masks. The exposed silicon nitride layer is selectively removed, wherein the protective dielectric layer when the sidewall spacers include the exposed silicon nitride layer, or a replacement protective dielectric layer formed directly on the semiconductor surface after ion implanting when the LDD or S/D regions include the exposed silicon nitride layer, protects the LDD or S/D regions from dopant loss due to etching during selectively removing.
摘要翻译： 一种在半导体表面上去除氮化硅以形成浅结的方法。 侧壁间隔物沿着栅堆叠的侧壁形成，其一起限定轻掺杂漏极（LDD）区域或源极/漏极（S / D）区域。 侧壁间隔物，LDD区域和S / D区域中的至少一个包括暴露的氮化硅层。 LDD或S / D区域包括直接形成在半导体表面上的保护电介质层。 离子注入使用侧壁间隔物作为植入物掩模来植入LDD区域或S / D区域。 暴露的氮化硅层被选择性地去除，其中当侧壁间隔物包括暴露的氮化硅层时的保护电介质层，或者当LDD或S / D区域包括 暴露的氮化硅层，在选择性去除期间由于蚀刻而保护LDD或S / D区域免受掺杂剂损失。
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公开(公告)号：US20120108027A1
公开(公告)日：2012-05-03
申请号：US13287671
申请日：2011-11-02
申请人： Weize Xiong , Deborah J. Riley
发明人： Weize Xiong , Deborah J. Riley
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/28518 , H01L21/823468 , H01L29/665 , H01L29/6653
摘要： A process for forming an integrated circuit with reduced sidewall spacers to enable improved silicide formation between minimum spaced transistor gates. A process for forming an integrated circuit with reduced sidewall spacers by first forming sidewall spacer by etching a sidewall dielectric and stopping on an etch stop layer, implanting source and drain dopants self aligned to the sidewall spacers, followed by removing a portion of the sidewall dielectric and removing the etch stop layer self aligned to the reduced sidewall spacers prior to forming silicide.
摘要翻译： 用于形成具有减少的侧壁间隔物的集成电路以使得能够改进最小间隔开的晶体管栅极之间的硅化物形成的工艺。 一种用于通过首先通过蚀刻侧壁电介质并停止在蚀刻停止层上形成侧壁间隔物来形成具有减小的侧壁间隔物的集成电路的工艺，将源极和漏极掺杂剂注入到与侧壁间隔物自对准，然后去除侧壁电介质的一部分 以及在形成硅化物之前去除与所述还原侧壁间隔物自对准的蚀刻停止层。
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公开(公告)号：US07422969B2
公开(公告)日：2008-09-09
申请号：US11861392
申请日：2007-09-26
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28088 , H01L21/32134 , H01L21/32136 , H01L21/32137 , H01L29/4966 , H01L29/6659
摘要： The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).
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6.发明申请METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING IMPROVED ACROSS CHIP IMPLANT UNIFORMITY 有权制造具有改进的切片植入均匀性的半导体器件的方法公开(公告)号：US20080153273A1
公开(公告)日：2008-06-26
申请号：US11615187
申请日：2006-12-22
IPC分类号： H01L21/425
CPC分类号： H01L21/823468 , H01L21/823418 , H01L21/823814 , H01L21/823864
摘要： The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, in one embodiment, includes forming a gate structure over a substrate, and forming a stack of layers on the substrate and at least partially along a sidewall of the gate structure. In this embodiment, the stack of layers includes an initial layer located over the substrate, a buffer layer located over the initial layer and an offset layer located over the buffer layer. This embodiment of the method further includes removing horizontal segments of the offset layer and the buffer layer using a dry etch and a wet clean, wherein removing includes choosing at least one of an initial thickness of the buffer layer, a period of time for the dry etch or a period of time for the wet clean such that horizontal segments of the initial layer are exposed and substantially unaffected after the dry etch and wet clean.
摘要翻译： 本发明提供一种制造半导体器件的方法。 在一个实施例中，用于制造半导体器件的方法包括在衬底上形成栅极结构，并且在衬底上并且至少部分地沿栅极结构的侧壁形成层叠层。 在该实施例中，层叠层包括位于衬底上的初始层，位于初始层之上的缓冲层和位于缓冲层上方的偏移层。 该方法的该实施例还包括使用干蚀刻和湿清洁来去除偏移层和缓冲层的水平段，其中移除包括选择缓冲层的初始厚度中的至少一个，干燥时间 蚀刻或湿式清洁的时间段，使得初始层的水平段在干蚀刻和湿清洁之后暴露并基本上不受影响。
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公开(公告)号：US08877581B2
公开(公告)日：2014-11-04
申请号：US12855736
申请日：2010-08-13
申请人： Amitabh Jain , Deborah J. Riley
发明人： Amitabh Jain , Deborah J. Riley
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/7848
摘要： An integrated circuit (IC) includes a plurality of strained metal oxide semiconductor (MOS) devices that include a semiconductor surface having a first doping type, a gate electrode stack over a portion of the semiconductor surface, and source/drain recesses that extend into the semiconductor surface and are framed by semiconductor surface interface regions on opposing sides of the gate stack. A first epitaxial strained alloy layer (rim) is on the semiconductor surface interface regions, and is doped with the first doping type. A second epitaxial strained alloy layer is on the rim and is doped with a second doping type that is opposite to the first doping type that is used to form source/drain regions.
摘要翻译： 集成电路（IC）包括多个应变金属氧化物半导体（MOS）器件，其包括具有第一掺杂类型的半导体表面，半导体表面的一部分上的栅极电极堆叠以及延伸到 半导体表面并且由栅堆叠的相对侧上的半导体表面界面区域构成。 第一外延应变合金层（边缘）在半导体表面界面区域上，并掺杂有第一掺杂型。 第二外延应变合金层位于边缘上并且掺杂有与用于形成源极/漏极区的第一掺杂类型相反的第二掺杂类型。
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8.发明授权Nitride removal while protecting semiconductor surfaces for forming shallow junctions 有权氮化物去除同时保护半导体表面以形成浅结公开(公告)号：US08043921B2
公开(公告)日：2011-10-25
申请号：US12731913
申请日：2010-03-25
IPC分类号： H01L21/336
CPC分类号： H01L21/2652 , H01L29/6653 , H01L29/6656
摘要： A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sidewall spacers, LDD regions and S/D regions include an exposed silicon nitride layer. The LDD or S/D regions include a protective dielectric layer formed directly on the semiconductor surface. Ion implanting implants the LDD regions or S/D regions using the sidewall spacers as implant masks. The exposed silicon nitride layer is selectively removed, wherein the protective dielectric layer when the sidewall spacers include the exposed silicon nitride layer, or a replacement protective dielectric layer formed directly on the semiconductor surface after ion implanting when the LDD or S/D regions include the exposed silicon nitride layer, protects the LDD or S/D regions from dopant loss due to etching during selectively removing.
摘要翻译： 一种在半导体表面上去除氮化硅以形成浅结的方法。 侧壁间隔物沿着栅堆叠的侧壁形成，其一起限定轻掺杂漏极（LDD）区域或源极/漏极（S / D）区域。 侧壁间隔物，LDD区域和S / D区域中的至少一个包括暴露的氮化硅层。 LDD或S / D区域包括直接形成在半导体表面上的保护电介质层。 离子注入使用侧壁间隔物作为植入物掩模来植入LDD区域或S / D区域。 暴露的氮化硅层被选择性地去除，其中当侧壁间隔物包括暴露的氮化硅层时的保护电介质层，或者当LDD或S / D区域包括 暴露的氮化硅层，在选择性去除期间由于蚀刻而保护LDD或S / D区域免受掺杂剂损失。
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公开(公告)号：US07323403B2
公开(公告)日：2008-01-29
申请号：US10999271
申请日：2004-11-29
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28088 , H01L21/32134 , H01L21/32136 , H01L21/32137 , H01L29/4966 , H01L29/6659
摘要： The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).
摘要翻译： 本发明提供了一种图案化金属栅电极的方法和包括其的集成电路的制造方法。 除了其他步骤之外，用于图案化金属栅电极的方法包括在位于衬底（110）上的栅极电介质层（210）上形成金属栅极电极层（220），并且使用 干蚀刻工艺（410）和湿蚀刻工艺（510）的组合。
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10.发明申请Method of Forming a CMOS Device with a Stressed-Channel NMOS Transistor and a Strained-Channel PMOS Transistor 有权用高压沟道NMOS晶体管和应变通道PMOS晶体管形成CMOS器件的方法公开(公告)号：US20140011340A1
公开(公告)日：2014-01-09
申请号：US13541957
申请日：2012-07-05
申请人： Seung-Chul Song , Amitabh Jain , Deborah J. Riley
发明人： Seung-Chul Song , Amitabh Jain , Deborah J. Riley
IPC分类号： H01L21/20
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L27/092 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7847 , H01L29/7848
摘要： A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.
摘要翻译： 形成应力通道NMOS晶体管和应变通道PMOS晶体管的方法在植入n型源极和漏极掺杂剂之前形成p型源极和漏极区，并且形成应力记忆层，由此减小施加到n - 沟道的PMOS晶体管。 此外，在形成p型源极和漏极区之后，但在植入n型掺杂剂之前，形成非导电层。 不导电层允许实现较浅的n型植入物，并且还用作应力记忆层的缓冲层。
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