公开(公告)号：US07812401B2

公开(公告)日：2010-10-12

申请号：US12688966

申请日：2010-01-18

申请人： Borna Obradovic ,  Shashank Ekbote ,  Mark Visokay

发明人： Borna Obradovic ,  Shashank Ekbote ,  Mark Visokay

IPC分类号： H01L27/092

CPC分类号： H01L29/7833 ,  H01L21/26513 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm−3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.

摘要翻译： 集成电路（IC）包括半导体衬底，形成在衬底中或衬底上的至少一个MOS晶体管，所述MOS晶体管包括掺杂有第一掺杂剂类型的源极和漏极，所述第一掺杂类型具有介于其间的第二掺杂剂类型的沟道区，以及 栅电极和沟道区上的栅极绝缘体。 形成低电阻接触的硅化物层位于源极和漏极的表面部分的界面区域。 在界面区域，第一掺杂剂的化学浓度为至少5×1020cm-3。 根据本发明的硅化物界面提供具有低硅化物界面电阻，低管密度的MOS晶体管，对短沟道行为具有可接受的小的影响。

公开(公告)号：US20090057759A1

公开(公告)日：2009-03-05

申请号：US11848962

申请日：2007-08-31

申请人： Borna Obradovic ,  Shashank Ekbote ,  Mark Visokay

发明人： Borna Obradovic ,  Shashank Ekbote ,  Mark Visokay

IPC分类号： H01L21/8238 ,  H01L29/94

CPC分类号： H01L29/7833 ,  H01L21/26513 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm−3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.

摘要翻译： 集成电路（IC）包括半导体衬底，形成在衬底中或衬底上的至少一个MOS晶体管，所述MOS晶体管包括掺杂有第一掺杂剂类型的源极和漏极，所述第一掺杂类型具有介于其间的第二掺杂剂类型的沟道区，以及 栅电极和沟道区上的栅极绝缘体。 形成低电阻接触的硅化物层位于源极和漏极的表面部分的界面区域。 在界面区域，第一掺杂剂的化学浓度为至少5×10 20 cm -3。 根据本发明的硅化物界面提供具有低硅化物界面电阻，低管密度的MOS晶体管，对短沟道行为具有可接受的小的影响。

公开(公告)号：US07682892B2

公开(公告)日：2010-03-23

申请号：US11848962

申请日：2007-08-31

申请人： Borna Obradovic ,  Shashank Ekbote ,  Mark Visokay

发明人： Borna Obradovic ,  Shashank Ekbote ,  Mark Visokay

IPC分类号： H01L21/8238

CPC分类号： H01L29/7833 ,  H01L21/26513 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5×1020 cm−3. Silicide interfaces according to the invention provide MOS transistor with a low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.

公开(公告)号：US20080044957A1

公开(公告)日：2008-02-21

申请号：US11870631

申请日：2007-10-11

申请人： James Chambers ,  Mark Visokay ,  Luigi Colombo ,  Antonio Rotondaro

发明人： James Chambers ,  Mark Visokay ,  Luigi Colombo ,  Antonio Rotondaro

IPC分类号： H01L21/84

CPC分类号： H01L21/823842

摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.

摘要翻译： 公开了具有不同功函数的金属栅极晶体管。 在一个示例中，第一金属是“中间间隙”金属，分别在第一和第二区域中被第二和第三金属操纵，以在不同区域中沿相反方向移动第一金属的功函数。 在不同区域中产生的功函数对应于将要形成的不同类型的晶体管。

公开(公告)号：US20070122962A1

公开(公告)日：2007-05-31

申请号：US11620447

申请日：2007-01-05

申请人： James Chambers ,  Mark Visokay ,  Luigi Colombo

发明人： James Chambers ,  Mark Visokay ,  Luigi Colombo

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823842 ,  Y10S438/981

摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An I/O dielectric layer is formed in core and I/O regions of a semiconductor device (506). The I/O dielectric layer is removed (508) from the core region of the device. A core dielectric layer is formed in the core region (510). A barrier layer is deposited and patterned to expose the NMOS devices of the core region (512). The core dielectric layer is removed from the core NMOS devices (514). A high-k dielectric layer is formed (514) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions/devices of the core region and the NMOS and PMOS regions/devices of the I/O region.

摘要翻译： 本发明通过提供在NMOS区内选择性地形成高k电介质层的制造方法来促进半导体制造。 在半导体器件（506）的芯和I / O区域中形成I / O电介质层。 从器件的芯区域去除（508）I / O电介质层。 在芯区域（510）中形成芯介质层。 屏蔽层被沉积并图案化以暴露核心区域（512）的NMOS器件。 从核心NMOS器件（514）去除芯介质层。 在核心和I / O区域上形成高k电介质层（514）。 然后，从核心区域的PMOS区域/器件和I / O区域的NMOS和PMOS区域/器件去除高k电介质层（512）。

公开(公告)号：US20070037343A1

公开(公告)日：2007-02-15

申请号：US11200741

申请日：2005-08-10

申请人： Luigi Colombo ,  James Chambers ,  Mark Visokay

发明人： Luigi Colombo ,  James Chambers ,  Mark Visokay

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L29/66545

摘要： The present invention provides a method of forming a dual work function metal gate microelectronics device 200. In one aspect, the method includes forming nMOS and pMOS stacked gate structures 315a and 315b. The nMOS and pMOS stacked gate structures 315a and 315b each comprise a gate dielectric 205, a first metal layer, 305 located over the gate dielectric 205 and a sacrificial gate layer 310 located over the first metal layer 305. The method further includes removing the sacrificial gate layer 310 in at least one of the nMOS or pMOS stacked gate structures, thereby forming a gate opening 825 and modifying the first metal layer 305 within the gate opening 825 to form a gate electrode with a desired work function.

公开(公告)号：US07037730B2

公开(公告)日：2006-05-02

申请号：US09904112

申请日：2001-07-11

申请人： Cem Basceri ,  Gurtej S. Sandhu ,  Mark Visokay

发明人： Cem Basceri ,  Gurtej S. Sandhu ,  Mark Visokay

IPC分类号： H01L21/8242

CPC分类号： H01L28/56 ,  H01L27/10811

摘要： Stabilized capacitors and DRAM cells using high dielectric constant oxide dielectric materials such as Ta2O5 and BaxSr(1−x)TiO3, and methods of making such capacitors and DRAM cells are provided. A preferred method includes providing a conductive oxide electrode, depositing a first layer of a high dielectric constant oxide dielectric material on the conductive oxide electrode, oxidizing the conductive oxide electrode and the first layer of the high dielectric constant oxide dielectric material under oxidizing conditions, depositing a second layer of the high dielectric constant oxide dielectric material on the first layer of the dielectric, and depositing an upper layer electrode on the second layer of the high dielectric constant oxide dielectric material.

摘要翻译： 使用高介电常数氧化物介电材料如Ta 2 O 5和Ba x Sr（1-x）的稳定电容器和DRAM单元 ）和提供制造这种电容器和DRAM单元的方法。 优选的方法包括提供导电氧化物电极，在导电氧化物电极上沉积高介电常数氧化物介电材料的第一层，在氧化条件下氧化导电氧化物电极和高介电常数氧化物介电材料的第一层，沉积 在所述电介质的第一层上的所述高介电常数氧化物电介质材料的第二层，以及在所述高介电常数氧化物介电材料的第二层上沉积上层电极。

公开(公告)号：US20060043524A1

公开(公告)日：2006-03-02

申请号：US11221103

申请日：2005-09-07

申请人： Mark Visokay ,  James Chambers

发明人： Mark Visokay ,  James Chambers

IPC分类号： H01L29/00

CPC分类号： H01L29/7831 ,  H01L29/66484

摘要： The present invention provides a system for producing a triple-gate transistor segment (300), utilizing a standard semiconductor substrate (302). The substrate has a plurality of isolation regions (304) formed along its upper surface in a distally separate relationship, defining a channel region (306). A form structure (308) is disposed atop the isolation regions, and defines a channel body area (310) over the channel region. A channel body structure (316) is disposed within the channel body area, and is engineered to provide a blunted corner or edge (318) along a perimeter of its upper exposed surface. The form structure is then removed, and subsequent processing is performed.

公开(公告)号：US20050136589A1

公开(公告)日：2005-06-23

申请号：US10738958

申请日：2003-12-17

申请人： Antonio Rotondaro ,  Douglas Mercer ,  Luigi Colombo ,  Mark Visokay ,  Haowen Bu ,  Malcolm Bevan

发明人： Antonio Rotondaro ,  Douglas Mercer ,  Luigi Colombo ,  Mark Visokay ,  Haowen Bu ,  Malcolm Bevan

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/51

CPC分类号： H01L21/28176 ,  H01L21/28194 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659

摘要： Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers not below gates and covers exposed portions (e.g., sidewalls) of high-k dielectric layers during fabrication with an encapsulation layer, which mitigates defects in the high-k dielectric layers and contamination of process tools. The encapsulation layer can also be employed as an etch stop layer and, at least partially, in comprising sidewall spacers. As a result, a semiconductor device can be fabricated with a substantially uniform equivalent oxide thickness.

摘要翻译： 公开了制造具有高k电介质层的半导体器件的方法。 本发明除了不在门下方的沉积的高k电介质层的部分，并且在用封装层制造期间覆盖高k电介质层的暴露部分（例如，侧壁），这减轻了高k电介质层中的缺陷和工艺污染 工具 封装层也可以用作蚀刻停止层，并且至少部分地包括侧壁间隔物。 结果，可以制造具有基本均匀的等效氧化物厚度的半导体器件。

公开(公告)号：US20050124121A1

公开(公告)日：2005-06-09

申请号：US10731647

申请日：2003-12-09

申请人： Antonio Rotondaro ,  James Chambers ,  Mark Visokay ,  Luigi Colombo

发明人： Antonio Rotondaro ,  James Chambers ,  Mark Visokay ,  Luigi Colombo

IPC分类号： C23C16/56 ,  H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8242 ,  H01L29/51

CPC分类号： H01L21/02318 ,  C23C16/56 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention pertains to annealing a high dielectric constant (high-k) material in a manner that substantially reduces or eliminates disadvantages and problems heretofore associated with the same. In particular, the high-k material is annealed in an ambient having a single chemistry of nitrogen and hydrogen, such as ammonia (NH3), to nitride and react unwanted impurities, and an oxidizer to oxidize and densify the high-k material, while mitigating growth of a lower-k material at an interface of the high-k material and an underlying substrate. Additionally, particular temperatures and pressures are utilized within the process so that the risk of an undesired exothermic reaction is mitigated. Annealing the high-k material in accordance with manners disclosed herein has application to semiconductor fabrication processes and, as such, is discussed herein within the context of the same.

摘要翻译： 本发明涉及以大大减少或消除与之相关的缺点和问题的方式退火高介电常数（高k）材料。 特别地，高k材料在具有氮和氢的单一化学性质（例如氨（NH 3））的环境中退火至氮化物并反应不需要的杂质，以及氧化剂氧化和 致密化高k材料，同时减轻在高k材料和下层衬底的界面处的较低k材料的生长。 此外，在该方法中利用特定的温度和压力，以便减轻不期望的放热反应的风险。 根据本文公开的方式对高k材料进行退火，已经应用于半导体制造工艺，并且因此本文在其上下文中讨论。